From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: brian.cain@oss.qualcomm.com, philmd@linaro.org,
ltaylorsimpson@gmail.com, matheus.bernardino@oss.qualcomm.com,
marco.liebel@oss.qualcomm.com, quic_mburton@quicinc.com,
sid.manning@oss.qualcomm.com, ale@rev.ng, anjo@rev.ng,
Brian Cain <bcain@quicinc.com>
Subject: [PATCH v5 07/35] target/hexagon: Make gen_exception_end_tb non-static
Date: Tue, 10 Mar 2026 20:48:55 -0700 [thread overview]
Message-ID: <20260311034923.1044737-8-brian.cain@oss.qualcomm.com> (raw)
In-Reply-To: <20260311034923.1044737-1-brian.cain@oss.qualcomm.com>
From: Brian Cain <bcain@quicinc.com>
Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
target/hexagon/translate.h | 2 ++
target/hexagon/translate.c | 4 ++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index b37cb492381..2804e08ce57 100644
--- a/target/hexagon/translate.h
+++ b/target/hexagon/translate.h
@@ -282,6 +282,8 @@ extern TCGv hex_vstore_addr[VSTORES_MAX];
extern TCGv hex_vstore_size[VSTORES_MAX];
extern TCGv hex_vstore_pending[VSTORES_MAX];
+void hex_gen_exception_end_tb(DisasContext *ctx, int excp);
+
void process_store(DisasContext *ctx, int slot_num);
FIELD(PROBE_PKT_SCALAR_STORE_S0, MMU_IDX, 0, 2)
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 8a223f6e13e..18b38c285ed 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -189,7 +189,7 @@ static void gen_end_tb(DisasContext *ctx)
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_exception_end_tb(DisasContext *ctx, int excp)
+void hex_gen_exception_end_tb(DisasContext *ctx, int excp)
{
gen_exec_counters(ctx);
tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->next_PC);
@@ -590,7 +590,7 @@ static void gen_insn(DisasContext *ctx)
ctx->insn->generate(ctx);
mark_store_width(ctx);
} else {
- gen_exception_end_tb(ctx, HEX_CAUSE_INVALID_OPCODE);
+ hex_gen_exception_end_tb(ctx, HEX_CAUSE_INVALID_OPCODE);
}
}
--
2.34.1
next prev parent reply other threads:[~2026-03-11 3:55 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-11 3:48 [PATCH v5 00/35] Hexagon system emulation, Part 1/3 Brian Cain
2026-03-11 3:48 ` [PATCH v5 01/35] docs: Add hexagon sysemu docs Brian Cain
2026-03-11 3:48 ` [PATCH v5 02/35] docs/system: Add hexagon CPU emulation Brian Cain
2026-03-11 3:48 ` [PATCH v5 03/35] target/hexagon: Fix badva reference, delete CAUSE Brian Cain
2026-03-11 3:48 ` [PATCH v5 04/35] target/hexagon: Add missing A_CALL attr, hintjumpr to multi_cof Brian Cain
2026-03-11 3:48 ` [PATCH v5 05/35] target/hexagon: Handle system/guest registers in gen_analyze_funcs.py and hex_common.py Brian Cain
2026-03-11 3:48 ` [PATCH v5 06/35] target/hexagon: Suppress unused-variable warnings for sysemu source regs Brian Cain
2026-03-12 21:03 ` Taylor Simpson
2026-03-11 3:48 ` Brian Cain [this message]
2026-03-11 3:48 ` [PATCH v5 08/35] target/hexagon: Switch to tag_ignore(), generate via get_{user, sys}_tags() Brian Cain via qemu development
2026-03-11 3:48 ` [PATCH v5 09/35] target/hexagon: Add privilege check, use tag_ignore() Brian Cain
2026-03-11 3:48 ` [PATCH v5 10/35] target/hexagon: Add a placeholder fp exception Brian Cain
2026-03-11 3:48 ` [PATCH v5 11/35] target/hexagon: Add guest, system reg number defs Brian Cain
2026-03-11 3:49 ` [PATCH v5 12/35] target/hexagon: Add guest, system reg number state Brian Cain
2026-03-11 3:49 ` [PATCH v5 13/35] target/hexagon: Add TCG values for sreg, greg Brian Cain
2026-03-11 3:49 ` [PATCH v5 14/35] target/hexagon: Add guest/sys reg writes to DisasContext Brian Cain
2026-03-11 3:49 ` [PATCH v5 15/35] target/hexagon: Add imported macro, attr defs for sysemu Brian Cain
2026-03-11 3:49 ` [PATCH v5 16/35] target/hexagon: Add new macro definitions " Brian Cain
2026-03-11 3:49 ` [PATCH v5 17/35] target/hexagon: Add handlers for guest/sysreg r/w Brian Cain
2026-03-11 3:49 ` [PATCH v5 18/35] target/hexagon: Add placeholder greg/sreg r/w helpers Brian Cain
2026-03-11 3:49 ` [PATCH v5 19/35] target/hexagon: Add vmstate representation Brian Cain
2026-03-25 19:21 ` Philippe Mathieu-Daudé
2026-03-11 3:49 ` [PATCH v5 20/35] target/hexagon: Make A_PRIV, "J2_trap*" insts need_env() Brian Cain
2026-03-11 3:49 ` [PATCH v5 21/35] target/hexagon: Define register fields for system regs Brian Cain
2026-03-11 3:49 ` [PATCH v5 22/35] target/hexagon: Implement do_raise_exception() Brian Cain
2026-03-11 3:49 ` [PATCH v5 23/35] target/hexagon: Add system reg insns Brian Cain
2026-03-11 3:49 ` [PATCH v5 24/35] target/hexagon: Add sysemu TCG overrides Brian Cain
2026-03-25 19:24 ` Philippe Mathieu-Daudé
2026-03-11 3:49 ` [PATCH v5 25/35] target/hexagon: Add implicit attributes to sysemu macros Brian Cain
2026-03-11 3:49 ` [PATCH v5 26/35] target/hexagon: Add TCG overrides for int handler insts Brian Cain
2026-03-11 3:49 ` [PATCH v5 27/35] target/hexagon: Add TCG overrides for thread ctl Brian Cain
2026-03-11 3:49 ` [PATCH v5 28/35] target/hexagon: Add TCG overrides for rte, nmi Brian Cain
2026-03-11 3:49 ` [PATCH v5 29/35] target/hexagon: Add sreg_{read,write} helpers Brian Cain
2026-03-25 19:26 ` Philippe Mathieu-Daudé
2026-03-11 3:49 ` [PATCH v5 30/35] target/hexagon: Add cpu modes, mmu indices, next_PC to state Brian Cain
2026-03-11 3:49 ` [PATCH v5 31/35] hw/hexagon: Introduce hexagon TLB device Brian Cain
2026-03-25 19:38 ` Philippe Mathieu-Daudé
2026-03-11 3:49 ` [PATCH v5 32/35] target/hexagon: Add stubs for modify_ssr/get_exe_mode Brian Cain
2026-03-11 3:49 ` [PATCH v5 33/35] target/hexagon: Add clear_wait_mode() definition Brian Cain
2026-03-11 3:49 ` [PATCH v5 34/35] target/hexagon: Define f{S,G}ET_FIELD macros Brian Cain
2026-03-11 3:49 ` [PATCH v5 35/35] target/hexagon: Add hex_interrupts support Brian Cain
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