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From: Jamin Lin <jamin_lin@aspeedtech.com>
To: "Cédric Le Goater" <clg@kaod.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Steven Lee" <steven_lee@aspeedtech.com>,
	"Troy Lee" <leetroy@gmail.com>,
	"Andrew Jeffery" <andrew@codeconstruct.com.au>,
	"Joel Stanley" <joel@jms.id.au>,
	"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: Jamin Lin <jamin_lin@aspeedtech.com>,
	Troy Lee <troy_lee@aspeedtech.com>,
	 Kane Chen <kane_chen@aspeedtech.com>,
	"flwu@google.com" <flwu@google.com>,
	 "nabihestefan@google.com" <nabihestefan@google.com>
Subject: [PATCH v1 11/13] hw/usb/hcd-ehci: Add descriptor address offset property
Date: Wed, 11 Mar 2026 07:26:29 +0000	[thread overview]
Message-ID: <20260311072614.1095587-12-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20260311072614.1095587-1-jamin_lin@aspeedtech.com>

When 64-bit addressing is supported, the Linux EHCI driver programs the
segment register to zero. See ehci_run function:
https://github.com/torvalds/linux/blob/master/drivers/usb/host/ehci-hcd.c

The driver comment also notes that descriptor structures allocated from
the DMA pool use segment zero semantics.

Descriptor memory is allocated using the DMA API. The platform driver
configures a 64-bit DMA mask so memory can be allocated above 4GB.
See ehci_platform_probe function:
https://github.com/torvalds/linux/blob/master/drivers/usb/host/ehci-platform.c

On AST2700 platforms, system DRAM is mapped above 4GB at 0x400000000.
As a result, descriptor addresses constructed directly from the guest
EHCI registers do not match the actual system address used by the
controller when fetching queue heads (QH) and queue element transfer
descriptors (qTD).

Introduce a descriptor-addr-offset property so platforms can provide an
address offset applied when constructing descriptor addresses. This
allows systems where DRAM resides above 4GB to correctly access EHCI
descriptors while keeping the default behavior unchanged for existing
machines.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/usb/hcd-ehci.h        | 1 +
 hw/usb/hcd-ehci-pci.c    | 2 ++
 hw/usb/hcd-ehci-sysbus.c | 2 ++
 hw/usb/hcd-ehci.c        | 1 +
 4 files changed, 6 insertions(+)

diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h
index a11d4179cd..6593480028 100644
--- a/hw/usb/hcd-ehci.h
+++ b/hw/usb/hcd-ehci.h
@@ -279,6 +279,7 @@ struct EHCIState {
     /* properties */
     uint32_t maxframes;
     bool caps_64bit_addr;
+    uint64_t descriptor_addr_offset;
 
     /*
      *  EHCI spec version 1.0 Section 2.3
diff --git a/hw/usb/hcd-ehci-pci.c b/hw/usb/hcd-ehci-pci.c
index 2ea8549db9..115d05ede0 100644
--- a/hw/usb/hcd-ehci-pci.c
+++ b/hw/usb/hcd-ehci-pci.c
@@ -139,6 +139,8 @@ static const Property ehci_pci_properties[] = {
     DEFINE_PROP_UINT32("maxframes", EHCIPCIState, ehci.maxframes, 128),
     DEFINE_PROP_BOOL("caps-64bit-addr", EHCIPCIState, ehci.caps_64bit_addr,
                      false),
+    DEFINE_PROP_UINT64("descriptor-addr-offset", EHCIPCIState,
+                       ehci.descriptor_addr_offset, 0),
 };
 
 static const VMStateDescription vmstate_ehci_pci = {
diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c
index 61215e9f3d..df138fb339 100644
--- a/hw/usb/hcd-ehci-sysbus.c
+++ b/hw/usb/hcd-ehci-sysbus.c
@@ -36,6 +36,8 @@ static const Property ehci_sysbus_properties[] = {
                      false),
     DEFINE_PROP_BOOL("caps-64bit-addr", EHCISysBusState, ehci.caps_64bit_addr,
                      false),
+    DEFINE_PROP_UINT64("descriptor-addr-offset", EHCISysBusState,
+                       ehci.descriptor_addr_offset, 0),
 };
 
 static void usb_ehci_sysbus_realize(DeviceState *dev, Error **errp)
diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c
index d9d1ac2d28..cdb53be4ae 100644
--- a/hw/usb/hcd-ehci.c
+++ b/hw/usb/hcd-ehci.c
@@ -155,6 +155,7 @@ static uint64_t ehci_get_desc_addr(EHCIState *s, uint32_t low)
         addr |= (uint64_t)s->ctrldssegment << 32;
     }
 
+    addr += s->descriptor_addr_offset;
     return addr;
 }
 
-- 
2.43.0


  parent reply	other threads:[~2026-03-11  7:29 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-11  7:26 [PATCH v1 00/13] hw/usb/ehci: Add 64-bit descriptor addressing support Jamin Lin
2026-03-11  7:26 ` [PATCH v1 01/13] hw/usb/hcd-ehci.h: Fix coding style issues reported by checkpatch Jamin Lin
2026-03-11  7:26 ` [PATCH v1 02/13] hw/usb/hcd-ehci.c: " Jamin Lin
2026-03-11  7:26 ` [PATCH v1 03/13] hw/usb/hcd-ehci: Change descriptor addresses to 64-bit Jamin Lin
2026-03-11  7:26 ` [PATCH v1 04/13] hw/usb/trace-events: Print EHCI queue and transfer addresses as 64-bit Jamin Lin
2026-03-11  7:26 ` [PATCH v1 05/13] hw/usb/hcd-ehci: Add property to advertise 64-bit addressing capability Jamin Lin
2026-03-11  7:26 ` [PATCH v1 06/13] hw/usb/hcd-ehci: Reject CTRLDSSEGMENT writes without 64-bit capability Jamin Lin
2026-03-11  7:26 ` [PATCH v1 07/13] hw/usb/hcd-ehci: Implement 64-bit QH descriptor addressing Jamin Lin
2026-03-11  7:26 ` [PATCH v1 08/13] hw/usb/hcd-ehci: Implement 64-bit qTD " Jamin Lin
2026-03-11  7:26 ` [PATCH v1 09/13] hw/usb/hcd-ehci: Implement 64-bit iTD " Jamin Lin
2026-03-11  7:26 ` [PATCH v1 10/13] hw/usb/hcd-ehci: Implement 64-bit siTD " Jamin Lin
2026-03-11  7:26 ` Jamin Lin [this message]
2026-03-11  7:26 ` [PATCH v1 12/13] hw/arm/aspeed_ast27x0: Enable 64-bit EHCI DMA addressing Jamin Lin
2026-03-11  7:26 ` [PATCH v1 13/13] hw/arm/aspeed_ast27x0: Set EHCI descriptor address offset Jamin Lin

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