Re: [PATCH 45/65] target/arm: GICv5 cpuif: Implement ICC_HPPIR_EL1

[Jonathan Cameron via qemu development <qemu-devel@nongnu.org>]

On Mon, 23 Feb 2026 17:01:52 +0000
Peter Maydell <peter.maydell@linaro.org> wrote:

> Implement ICC_HPPIR_EL1, which the guest can use to read the current
> highest priority pending interrupt.  Like APR, PCR and CR0, this is
> banked, with the _EL1 register reading the answer for the current
> logical interrupt domain, and the _EL3 register reading the answer
> for the EL3 interrupt domain.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Few formatting things...

Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>

> ---
>  hw/intc/arm_gicv5.c                | 11 ++++++
>  include/hw/intc/arm_gicv5_stream.h | 14 +++++++
>  target/arm/tcg/gicv5-cpuif.c       | 62 ++++++++++++++++++++++++++++++
>  3 files changed, 87 insertions(+)
> 
> diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c
> index 070d414d67..6cb81123e5 100644
> --- a/hw/intc/arm_gicv5.c
> +++ b/hw/intc/arm_gicv5.c
> @@ -527,6 +527,17 @@ static void irs_recall_hppis(GICv5 *s, GICv5Domain domain)
>      }
>  }
>  
> +GICv5PendingIrq gicv5_get_hppi(GICv5Common *cs, GICv5Domain domain,
> +                               uint32_t iaffid)
> +{
> +    GICv5 *s = ARM_GICV5(cs);
> +

Why the blank line?

> +    int cpuidx = irs_cpuidx_from_iaffid(cs, iaffid);
> +
> +    assert(cpuidx >= 0);
> +    return s->hppi[domain][cpuidx];
> +}
> +
>  static hwaddr l1_iste_addr(GICv5Common *cs, const GICv5ISTConfig *cfg,
>                             uint32_t id)
>  {

> diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c
> index 45ef80ca87..adb4d2018f 100644
> --- a/target/arm/tcg/gicv5-cpuif.c
> +++ b/target/arm/tcg/gicv5-cpuif.c

>  /*
>   * We implement 24 bits of interrupt ID, the mandated 5 bits of priority,
>   * and no legacy GICv3.3 vcpu interface (yet)
> @@ -114,6 +118,52 @@ static uint64_t gic_running_prio(CPUARMState *env, GICv5Domain domain)
>      return hap < 32 ? hap : PRIO_IDLE;
>  }
>  
> +static GICv5PendingIrq gic_hppi(CPUARMState *env, GICv5Domain domain)
> +{
> +    /*
> +     * Return the current highest priority pending

rewrap

> +     * interrupt for the specified domain, if it has sufficient
> +     * priority to preempt. The intid field of the return value
> +     * will be in the format of the ICC_HPPIR register (and will
> +     * be zero if and only if there is no interrupt that can preempt).
> +     */
> +
> +    GICv5Common *gic = gicv5_get_gic(env);
> +    GICv5PendingIrq best;
> +    GICv5PendingIrq irs_hppi;

Maybe just one line?

> +
> +    if (!(env->gicv5_cpuif.icc_cr0[domain] & R_ICC_CR0_EN_MASK)) {
> +        /* If cpuif is disabled there is no HPPI */
> +        return (GICv5PendingIrq) { .intid = 0, .prio = PRIO_IDLE };
> +    }
> +
> +    irs_hppi = gicv5_get_hppi(gic, domain, env->gicv5_iaffid);
> +
> +    /*
> +     * If the best PPI and the best interrupt from the IRS have the
> +     * same priority, it's IMPDEF which we pick (R_VVBPS). We choose
> +     * the PPI.
> +     */
> +    if (env->gicv5_cpuif.ppi_hppi[domain].prio <= irs_hppi.prio) {
> +        best = env->gicv5_cpuif.ppi_hppi[domain];
> +    } else {
> +        best = irs_hppi;
> +    }
> +
> +    /*
> +     * D_MSQKF: an interrupt has sufficient priority if its priority
> +     * is higher than the current running priority and equal to or
> +     * higher than the priority mask.
> +     */
> +    if (best.prio == PRIO_IDLE ||
> +        best.prio > env->gicv5_cpuif.icc_pcr[domain] ||
> +        best.prio >= gic_running_prio(env, domain)) {
> +        return (GICv5PendingIrq) { .intid = 0, .prio = PRIO_IDLE };
> +    }
> +    best.intid |= R_ICC_HPPIR_EL1_HPPIV_MASK;
> +    return best;
> +}