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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b5189971asm6778525f8f.30.2026.03.18.03.33.12 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 18 Mar 2026 03:33:13 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Weiwei Li , Pierrick Bouvier , Warner Losh , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , Vijai Kumar K , Anton Johansson , Daniel Henrique Barboza , qemu-riscv@nongnu.org, Alistair Francis , Palmer Dabbelt , Jiaxun Yang , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Liu Zhiwei , Djordje Todorovic Subject: [PATCH-for-11.1 15/16] target/riscv: Use MO_LE for instruction fetch Date: Wed, 18 Mar 2026 11:31:20 +0100 Message-ID: <20260318103122.97244-16-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260318103122.97244-1-philmd@linaro.org> References: <20260318103122.97244-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Djordje Todorovic RISC-V instructions are always little-endian regardless of the data endianness mode configured via mstatus SBE/MBE/UBE bits. Currently, instruction fetches in decode_opc() and the page boundary check use mo_endian(ctx), which returns MO_TE. This happens to work today because RISC-V targets are little-endian only, but is semantically incorrect and will break once mo_endian() is updated to respect runtime data endianness for big-endian support. Use MO_LE explicitly for all instruction fetch paths. Data memory operations (AMOs, loads/stores via mxl_memop) continue to use mo_endian(ctx) as they should respect the configured data endianness. Not-Signed-off-by: Djordje Todorovic Reviewed-by: Alistair Francis Message-ID: <20260311115910.564481-3-djordje.todorovic@htecgroup.com> Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6f8b8e9d19a..5df5b738495 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1255,7 +1255,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx) * additional page fault. */ opcode = translator_ldl_end(env, &ctx->base, ctx->base.pc_next, - mo_endian(ctx)); + MO_LE); } else { /* * For unaligned pc, instruction preload may trigger additional @@ -1263,7 +1263,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx) */ opcode = (uint32_t) translator_lduw_end(env, &ctx->base, ctx->base.pc_next, - mo_endian(ctx)); + MO_LE); } ctx->ol = ctx->xl; @@ -1285,7 +1285,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx) opcode = deposit32(opcode, 16, 16, translator_lduw_end(env, &ctx->base, ctx->base.pc_next + 2, - mo_endian(ctx))); + MO_LE)); } ctx->opcode = opcode; @@ -1401,7 +1401,7 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) { uint16_t next_insn = translator_lduw_end(env, &ctx->base, ctx->base.pc_next, - mo_endian(ctx)); + MO_LE); int len = insn_len(next_insn); if (!translator_is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) { -- 2.53.0