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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Weiwei Li" <liwei1518@gmail.com>,
	"Pierrick Bouvier" <pierrick.bouvier@linaro.org>,
	"Warner Losh" <imp@bsdimp.com>,
	"Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr>,
	"Vijai Kumar K" <vijai@behindbytes.com>,
	"Anton Johansson" <anjo@rev.ng>,
	"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
	qemu-riscv@nongnu.org,
	"Alistair Francis" <Alistair.Francis@wdc.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
	"Djordje Todorovic" <Djordje.Todorovic@htecgroup.com>
Subject: [PATCH-for-11.1 08/16] target/riscv: Simplify riscv_cpu_gdb_write_register()
Date: Wed, 18 Mar 2026 11:31:13 +0100	[thread overview]
Message-ID: <20260318103122.97244-9-philmd@linaro.org> (raw)
In-Reply-To: <20260318103122.97244-1-philmd@linaro.org>

Use a single ldn() call, sign-extend once.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
Note I'm skeptical about 128-bit registers path, but this
would be a pre-existing issue.
---
 target/riscv/gdbstub.c | 25 ++++++-------------------
 1 file changed, 6 insertions(+), 19 deletions(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index be42566bcc8..a5c12638782 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -84,33 +84,20 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
-    int length = 0;
-    uint64_t tmp;
+    const size_t regsize = mcc->def->misa_mxl_max == MXL_RV32 ? 4 : 8;
+    uint64_t tmp = ldn(env, mem_buf, regsize);
 
-    switch (mcc->def->misa_mxl_max) {
-    case MXL_RV32:
-        tmp = (int32_t)ldn(env, mem_buf, 4);
-        length = 4;
-        break;
-    case MXL_RV64:
-    case MXL_RV128:
-        if (env->xl < MXL_RV64) {
-            tmp = (int32_t)ldn(env, mem_buf, 8);
-        } else {
-            tmp = ldn(env, mem_buf, 8);
-        }
-        length = 8;
-        break;
-    default:
-        g_assert_not_reached();
+    if (env->xl < MXL_RV64) {
+        tmp = (int32_t)tmp;
     }
+
     if (n > 0 && n < 32) {
         env->gpr[n] = tmp;
     } else if (n == 32) {
         env->pc = tmp;
     }
 
-    return length;
+    return regsize;
 }
 
 static int riscv_gdb_get_fpu(CPUState *cs, GByteArray *buf, int n)
-- 
2.53.0



  parent reply	other threads:[~2026-03-18 10:33 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-18 10:31 [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Philippe Mathieu-Daudé
2026-03-18 10:31 ` [PATCH-for-11.1 01/16] hw/riscv: Mark RISC-V specific peripherals as little-endian Philippe Mathieu-Daudé
2026-03-19  1:43   ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 02/16] target/riscv: Use explicit little-endian LD/ST API Philippe Mathieu-Daudé
2026-03-19  3:09   ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 03/16] target/riscv: Make LQ and SQ use 128-bit ld/st Philippe Mathieu-Daudé
2026-03-26  2:06   ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 04/16] target/riscv: Remove MTTCG check for x-rv128 CPU model Philippe Mathieu-Daudé
2026-03-26  2:06   ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 05/16] target/riscv: Explode MO_TExx -> MO_TE | MO_xx (again) Philippe Mathieu-Daudé
2026-03-26  2:07   ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 06/16] target/riscv: Conceal MO_ALIGN|MO_TE within load_acquire / store_release Philippe Mathieu-Daudé
2026-03-26  2:08   ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 07/16] target/riscv: Factor tiny ldn() helper in gdbstub Philippe Mathieu-Daudé
2026-03-26  2:09   ` Alistair Francis
2026-03-18 10:31 ` Philippe Mathieu-Daudé [this message]
2026-03-26  2:12   ` [PATCH-for-11.1 08/16] target/riscv: Simplify riscv_cpu_gdb_write_register() Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 09/16] target/riscv: Expose mo_endian_env() Philippe Mathieu-Daudé
2026-03-26  2:13   ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 10/16] target/riscv: Have gdbstub consider CPU endianness Philippe Mathieu-Daudé
2026-03-26  2:15   ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 11/16] target/riscv: Replace MO_TE by mo_endian (MIPS extension) Philippe Mathieu-Daudé
2026-03-26  2:17   ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 12/16] target/riscv: Replace MO_TE by mo_endian (Zilsd extension) Philippe Mathieu-Daudé
2026-03-26  2:18   ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 13/16] target/riscv: Replace MO_TE by mo_endian (Zalasr extension) Philippe Mathieu-Daudé
2026-03-26  2:20   ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 14/16] target/riscv: Replace MO_TE -> MO_LE Philippe Mathieu-Daudé
2026-03-26  2:21   ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 15/16] target/riscv: Use MO_LE for instruction fetch Philippe Mathieu-Daudé
2026-03-20 11:27   ` Djordje Todorovic
2026-03-18 10:31 ` [PATCH-for-11.1 16/16] configs/targets: Forbid RISC-V to use legacy native endianness APIs Philippe Mathieu-Daudé
2026-03-26  2:21   ` Alistair Francis
2026-03-26  2:28 ` [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Alistair Francis

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