[PATCH 3/6] riscv: andes: Implement noncached memory using SBI PMA

[PATCH 3/6] riscv: andes: Implement noncached memory using SBI PMA

[Leo Yu-Chi Liang via qemu development]

Implement noncached memory region management for Andes RISC-V
platforms using SBI PMA (Physical Memory Attribute) calls:

- noncached_init(): Compute region below malloc area, probe PMA
  support via sbi_pma_probe(), then configure the region as
  non-cacheable bufferable using sbi_pma_set() with NAPOT and
  NON_CACHE_BUF flags.
- noncached_alloc(): Bump allocator from the noncached region.
- noncached_set_region(): No-op since PMA handles attributes.
- noncached_free(): Release PMA entry, with probe-before-free
  guard to avoid calling free on unsupported firmware.

Also call noncached_free() in cleanup_before_linux() before
cache_flush() so the PMA entry is released before handing off
to Linux.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
 arch/riscv/cpu/andes/Makefile   |  1 +
 arch/riscv/cpu/andes/cpu.c      |  3 ++
 arch/riscv/cpu/andes/noncache.c | 79 +++++++++++++++++++++++++++++++++
 include/cpu_func.h              |  1 +
 4 files changed, 84 insertions(+)
 create mode 100644 arch/riscv/cpu/andes/noncache.c

diff --git a/arch/riscv/cpu/andes/Makefile b/arch/riscv/cpu/andes/Makefile
index 35a1a2fb836..f3602f6f598 100644
--- a/arch/riscv/cpu/andes/Makefile
+++ b/arch/riscv/cpu/andes/Makefile
@@ -6,3 +6,4 @@
 obj-y	:= cpu.o
 obj-y	+= cache.o
 obj-y	+= spl.o
+obj-$(CONFIG_SYS_HAS_NONCACHED_MEMORY) += noncache.o
diff --git a/arch/riscv/cpu/andes/cpu.c b/arch/riscv/cpu/andes/cpu.c
index feb755a4f0d..3aa89d86b6b 100644
--- a/arch/riscv/cpu/andes/cpu.c
+++ b/arch/riscv/cpu/andes/cpu.c
@@ -22,6 +22,9 @@ int cleanup_before_linux(void)
 {
 	disable_interrupts();
 
+	if (IS_ENABLED(CONFIG_SYS_HAS_NONCACHED_MEMORY))
+		noncached_free();
+
 	cache_flush();
 
 	return 0;
diff --git a/arch/riscv/cpu/andes/noncache.c b/arch/riscv/cpu/andes/noncache.c
new file mode 100644
index 00000000000..9886a757620
--- /dev/null
+++ b/arch/riscv/cpu/andes/noncache.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2026 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#include <cpu_func.h>
+#include <log.h>
+#include <malloc.h>
+#include <asm/sbi.h>
+#include <asm/system.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+static unsigned long noncached_start;
+static unsigned long noncached_end;
+static unsigned long noncached_next;
+
+void noncached_set_region(void)
+{
+}
+
+int noncached_init(void)
+{
+	phys_addr_t start, end;
+	size_t size;
+	int ret;
+
+	/* If this calculation changes, update board_f.c:reserve_noncached() */
+	end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
+	size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
+	start = end - size;
+
+	debug("mapping memory %pa-%pa non-cached\n", &start, &end);
+
+	ret = sbi_pma_probe();
+	if (ret <= 0) {
+		debug("PMA probe failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = sbi_pma_set(start, size,
+			  ANDES_PMACFG_ETYP_NAPOT |
+			  ANDES_PMACFG_MTYP_MEM_NON_CACHE_BUF);
+	if (ret) {
+		debug("PMA set failed: %d\n", ret);
+		return ret;
+	}
+
+	noncached_start = start;
+	noncached_end = end;
+	noncached_next = start;
+
+	return 0;
+}
+
+phys_addr_t noncached_alloc(size_t size, size_t align)
+{
+	phys_addr_t next = ALIGN(noncached_next, align);
+
+	if (next >= noncached_end || (noncached_end - next) < size)
+		return 0;
+
+	debug("allocated %zu bytes of uncached memory @%pa\n", size, &next);
+	noncached_next = next + size;
+
+	return next;
+}
+
+void noncached_free(void)
+{
+	if (!noncached_start)
+		return;
+
+	if (sbi_pma_probe() <= 0)
+		return;
+
+	sbi_pma_free(noncached_start);
+}
diff --git a/include/cpu_func.h b/include/cpu_func.h
index 70a41ead3f7..061d497d454 100644
--- a/include/cpu_func.h
+++ b/include/cpu_func.h
@@ -100,6 +100,7 @@ int noncached_init(void);
 void noncached_set_region(void);
 
 phys_addr_t noncached_alloc(size_t size, size_t align);
+void noncached_free(void);
 
 enum {
 	/* Disable caches (else flush caches but leave them active) */
-- 
2.34.1

[PATCH 4/6] cache: andes-l2: Add writeback-invalidate operation

[Leo Yu-Chi Liang via qemu development]

Add a wbinval operation to the cache uclass that performs
writeback-invalidate without the disable/enable cycle that the
existing disable path uses. This is needed for flush_dcache_all()
to properly flush both L1 and L2 caches.

Implement andes_l2_wbinval_all() in the Andes L2 cache driver
which issues the L2_WBINVAL_ALL command while keeping the cache
enabled.

Update flush_dcache_all() in the Andes cache code to also call
L2 wbinval when CONFIG_ANDES_L2_CACHE is enabled.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
 arch/riscv/cpu/andes/cache.c   |  4 ++++
 drivers/cache/cache-andes-l2.c | 24 ++++++++++++++++++++++++
 drivers/cache/cache-uclass.c   | 10 ++++++++++
 include/cache.h                | 16 ++++++++++++++++
 4 files changed, 54 insertions(+)

diff --git a/arch/riscv/cpu/andes/cache.c b/arch/riscv/cpu/andes/cache.c
index bb57498d75a..3b325d77954 100644
--- a/arch/riscv/cpu/andes/cache.c
+++ b/arch/riscv/cpu/andes/cache.c
@@ -44,6 +44,10 @@ static void cache_ops(int (*ops)(struct udevice *dev))
 void flush_dcache_all(void)
 {
 	csr_write(CSR_UCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL);
+
+#ifdef CONFIG_ANDES_L2_CACHE
+	cache_ops(cache_wbinval);
+#endif
 }
 
 void flush_dcache_range(unsigned long start, unsigned long end)
diff --git a/drivers/cache/cache-andes-l2.c b/drivers/cache/cache-andes-l2.c
index 45a4f216b07..5ceccf609e5 100644
--- a/drivers/cache/cache-andes-l2.c
+++ b/drivers/cache/cache-andes-l2.c
@@ -91,6 +91,29 @@ static int andes_l2_enable(struct udevice *dev)
 	return 0;
 }
 
+static int andes_l2_wbinval_all(struct udevice *dev)
+{
+	struct andes_l2_plat *plat = dev_get_plat(dev);
+	volatile struct l2cache *regs = plat->regs;
+	u8 hart = gd->arch.boot_hart;
+
+	void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
+	void __iomem *cctlstatus = (void __iomem *)CCTL_STATUS_REG(regs, hart);
+
+	if ((regs) && (readl(&regs->control) & L2_ENABLE)) {
+		writel(L2_WBINVAL_ALL, cctlcmd);
+
+		while ((readl(cctlstatus) & CCTL_STATUS_MSK(hart))) {
+			if ((readl(cctlstatus) & CCTL_STATUS_ILLEGAL(hart))) {
+				printf("L2 flush illegal! hanging...");
+				hang();
+			}
+		}
+	}
+
+	return 0;
+}
+
 static int andes_l2_disable(struct udevice *dev)
 {
 	struct andes_l2_plat *plat = dev_get_plat(dev);
@@ -192,6 +215,7 @@ static const struct udevice_id andes_l2_cache_ids[] = {
 static const struct cache_ops andes_l2_cache_ops = {
 	.enable		= andes_l2_enable,
 	.disable	= andes_l2_disable,
+	.wbinval	= andes_l2_wbinval_all,
 };
 
 U_BOOT_DRIVER(andes_l2_cache) = {
diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c
index 300e7bc86e1..8e77c9e2f4e 100644
--- a/drivers/cache/cache-uclass.c
+++ b/drivers/cache/cache-uclass.c
@@ -38,6 +38,16 @@ int cache_disable(struct udevice *dev)
 	return ops->disable(dev);
 }
 
+int cache_wbinval(struct udevice *dev)
+{
+	struct cache_ops *ops = cache_get_ops(dev);
+
+	if (!ops->wbinval)
+		return -ENOSYS;
+
+	return ops->wbinval(dev);
+}
+
 UCLASS_DRIVER(cache) = {
 	.id		= UCLASS_CACHE,
 	.name		= "cache",
diff --git a/include/cache.h b/include/cache.h
index 296ae3c8b48..45b27ab989c 100644
--- a/include/cache.h
+++ b/include/cache.h
@@ -42,6 +42,14 @@ struct cache_ops {
 	 * @return 0 if OK, -ve on error
 	 */
 	int (*disable)(struct udevice *dev);
+
+	/**
+	 * wbinval() - Writeback and invalidate cache
+	 *
+	 * @dev:	Device to check (UCLASS_CACHE)
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*wbinval)(struct udevice *dev);
 };
 
 #define cache_get_ops(dev)	((struct cache_ops *)(dev)->driver->ops)
@@ -70,4 +78,12 @@ int cache_enable(struct udevice *dev);
  * Return: 0 if OK, -ve on error
  */
 int cache_disable(struct udevice *dev);
+
+/**
+ * cache_wbinval() - Writeback and invalidate cache
+ *
+ * @dev:	Device to check (UCLASS_CACHE)
+ * Return: 0 if OK, -ve on error
+ */
+int cache_wbinval(struct udevice *dev);
 #endif
-- 
2.34.1

[PATCH 5/6] net: ftmac100: Add noncached memory support for DMA descriptors

[Leo Yu-Chi Liang via qemu development]

Change TX and RX DMA descriptors from inline arrays embedded in
struct ftmac100_data to dynamically allocated pointers. When
CONFIG_SYS_NONCACHED_MEMORY is enabled, allocate descriptors from
the noncached memory region using noncached_alloc(); otherwise
fall back to memalign().

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
 drivers/net/ftmac100.c | 27 +++++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c
index fa0b3dbb6d1..f7f7db56130 100644
--- a/drivers/net/ftmac100.c
+++ b/drivers/net/ftmac100.c
@@ -30,8 +30,8 @@ DECLARE_GLOBAL_DATA_PTR;
 #define FTMAC100_MDIO_TIMEOUT_USEC     10000
 
 struct ftmac100_data {
-	struct ftmac100_txdes txdes[1];
-	struct ftmac100_rxdes rxdes[PKTBUFSRX];
+	struct ftmac100_txdes *txdes;
+	struct ftmac100_rxdes *rxdes;
 	int rx_index;
 	const char *name;
 	struct ftmac100 *ftmac100;
@@ -403,12 +403,35 @@ static int ftmac100_mdio_init(struct udevice *dev)
 	return 0;
 }
 
+static void *ftmac100_alloc_descs(unsigned int num, unsigned int size)
+{
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+	return (void *)noncached_alloc(num * size,
+				       ARCH_DMA_MINALIGN);
+#else
+	return memalign(ARCH_DMA_MINALIGN, num * size);
+#endif
+}
+
 static int ftmac100_probe(struct udevice *dev)
 {
 	struct ftmac100_data *priv = dev_get_priv(dev);
 	priv->name = dev->name;
 	int ret = 0;
 
+	priv->txdes = ftmac100_alloc_descs(1, sizeof(struct ftmac100_txdes));
+	if (!priv->txdes) {
+		dev_err(dev, "Failed to allocate tx descriptors\n");
+		return -ENOMEM;
+	}
+
+	priv->rxdes = ftmac100_alloc_descs(PKTBUFSRX,
+					   sizeof(struct ftmac100_rxdes));
+	if (!priv->rxdes) {
+		dev_err(dev, "Failed to allocate rx descriptors\n");
+		return -ENOMEM;
+	}
+
 	ret = ftmac100_mdio_init(dev);
 	if (ret) {
 		dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
-- 
2.34.1

[PATCH 6/6] configs: ae350: Enable noncached memory support

[Leo Yu-Chi Liang via qemu development]

Enable CONFIG_SYS_HAS_NONCACHED_MEMORY and set
CONFIG_SYS_NONCACHED_MEMORY to 1MB (0x100000) on all AE350
S-mode defconfigs where SBI is available:

  ae350_rv{32,64}_spl_defconfig
  ae350_rv{32,64}_spl_xip_defconfig
  ae350_rv{32,64}_falcon_defconfig
  ae350_rv{32,64}_falcon_xip_defconfig

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
 configs/ae350_rv32_falcon_defconfig     | 2 ++
 configs/ae350_rv32_falcon_xip_defconfig | 2 ++
 configs/ae350_rv32_spl_defconfig        | 2 ++
 configs/ae350_rv32_spl_xip_defconfig    | 2 ++
 configs/ae350_rv64_falcon_defconfig     | 2 ++
 configs/ae350_rv64_falcon_xip_defconfig | 2 ++
 configs/ae350_rv64_spl_defconfig        | 2 ++
 configs/ae350_rv64_spl_xip_defconfig    | 2 ++
 8 files changed, 16 insertions(+)

diff --git a/configs/ae350_rv32_falcon_defconfig b/configs/ae350_rv32_falcon_defconfig
index 659be8287ba..08d27d7c823 100644
--- a/configs/ae350_rv32_falcon_defconfig
+++ b/configs/ae350_rv32_falcon_defconfig
@@ -53,6 +53,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_FTMAC100=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_SYS_NONCACHED_MEMORY=0x100000
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv32_falcon_xip_defconfig b/configs/ae350_rv32_falcon_xip_defconfig
index 93b80ef789d..42f0d5f4e60 100644
--- a/configs/ae350_rv32_falcon_xip_defconfig
+++ b/configs/ae350_rv32_falcon_xip_defconfig
@@ -55,6 +55,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_FTMAC100=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_SYS_NONCACHED_MEMORY=0x100000
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig
index 4b0f52ff42b..146e3650708 100644
--- a/configs/ae350_rv32_spl_defconfig
+++ b/configs/ae350_rv32_spl_defconfig
@@ -53,6 +53,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_FTMAC100=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_SYS_NONCACHED_MEMORY=0x100000
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig
index f076f36c73c..c994331e75f 100644
--- a/configs/ae350_rv32_spl_xip_defconfig
+++ b/configs/ae350_rv32_spl_xip_defconfig
@@ -54,6 +54,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_FTMAC100=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_SYS_NONCACHED_MEMORY=0x100000
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv64_falcon_defconfig b/configs/ae350_rv64_falcon_defconfig
index c7c44671419..5dd58047aeb 100644
--- a/configs/ae350_rv64_falcon_defconfig
+++ b/configs/ae350_rv64_falcon_defconfig
@@ -53,6 +53,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_FTMAC100=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_SYS_NONCACHED_MEMORY=0x100000
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv64_falcon_xip_defconfig b/configs/ae350_rv64_falcon_xip_defconfig
index ae9c7cfd933..78e1ea118ac 100644
--- a/configs/ae350_rv64_falcon_xip_defconfig
+++ b/configs/ae350_rv64_falcon_xip_defconfig
@@ -55,6 +55,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_FTMAC100=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_SYS_NONCACHED_MEMORY=0x100000
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig
index af000ca58ce..22c710661e0 100644
--- a/configs/ae350_rv64_spl_defconfig
+++ b/configs/ae350_rv64_spl_defconfig
@@ -53,6 +53,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_FTMAC100=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_SYS_NONCACHED_MEMORY=0x100000
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig
index 8c6e2773723..d2b29c19397 100644
--- a/configs/ae350_rv64_spl_xip_defconfig
+++ b/configs/ae350_rv64_spl_xip_defconfig
@@ -54,6 +54,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_FTMAC100=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_SYS_NONCACHED_MEMORY=0x100000
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
-- 
2.34.1