[PATCH 0/8] target/ppc: Forbid to use legacy ldst_phys() API

[PATCH 0/8] target/ppc: Forbid to use legacy ldst_phys() API

[Philippe Mathieu-Daudé]

Replace legacy ld/st_phys() by address_space_ld/st()
then lock the target again further legacy API uses.

Philippe Mathieu-Daudé (8):
  hw/ppc/spapr: Un-inline rtas_load/store() helpers
  target/ppc: Factor common ppc_load_epr() helper out
  target/ppc/mmu: Remove unused hash32_store_hpte() helpers
  target/ppc/mmu: Restrict hash32_load_hpte() helpers scope
  target/ppc/mmu: Replace legacy ld/st_phys() -> address_space_ld/st()
  hw/ppc/pegasos: Introduce rtas_ldl() / rtas_stl() helpers
  hw/ppc/pegasos: Replace legacy ld/st_phys() -> address_space_ld/st()
  configs/targets: Restrict the legacy ldst_phys() API on PPC

 configs/targets/ppc-softmmu.mak |  1 +
 include/hw/ppc/spapr.h          | 18 ++-------
 target/ppc/cpu.h                |  2 +
 target/ppc/mmu-hash32.h         | 32 ----------------
 hw/ppc/pegasos.c                | 67 +++++++++++++++++++--------------
 hw/ppc/spapr_rtas.c             | 15 ++++++++
 target/ppc/cpu.c                |  9 +++++
 target/ppc/excp_helper.c        |  3 +-
 target/ppc/kvm.c                |  2 +-
 target/ppc/mmu-hash32.c         | 24 +++++++++++-
 10 files changed, 93 insertions(+), 80 deletions(-)

-- 
2.53.0

[PATCH 1/8] hw/ppc/spapr: Un-inline rtas_load/store() helpers

[Philippe Mathieu-Daudé]

The 32-bit binary doesn't use these helpers, so don't need to
compile them. Rather than using 64-bit target #ifdef'ry in a
global header, un-inline the calls since the helpers are called
from I/O (cold) path.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/ppc/spapr.h | 18 +++---------------
 hw/ppc/spapr_rtas.c    | 15 +++++++++++++++
 2 files changed, 18 insertions(+), 15 deletions(-)

diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index b022f8dd25d..9acda15d4f6 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -796,21 +796,9 @@ static inline uint64_t ppc64_phys_to_real(uint64_t addr)
     return addr & ~0xF000000000000000ULL;
 }
 
-static inline uint32_t rtas_ld(target_ulong phys, int n)
-{
-    return ldl_be_phys(&address_space_memory,
-                       ppc64_phys_to_real(phys + 4 * n));
-}
-
-static inline uint64_t rtas_ldq(target_ulong phys, int n)
-{
-    return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1);
-}
-
-static inline void rtas_st(target_ulong phys, int n, uint32_t val)
-{
-    stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4 * n), val);
-}
+uint32_t rtas_ld(target_ulong phys, int n);
+uint64_t rtas_ldq(target_ulong phys, int n);
+void rtas_st(target_ulong phys, int n, uint32_t val);
 
 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm,
                               uint32_t token,
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index cb79ad34053..0871425237e 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -52,6 +52,21 @@
 #include "migration/blocker.h"
 #include "helper_regs.h"
 
+uint32_t rtas_ld(target_ulong phys, int n)
+{
+    return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4 * n));
+}
+
+uint64_t rtas_ldq(target_ulong phys, int n)
+{
+    return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1);
+}
+
+void rtas_st(target_ulong phys, int n, uint32_t val)
+{
+    stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4 * n), val);
+}
+
 static void rtas_display_character(PowerPCCPU *cpu, SpaprMachineState *spapr,
                                    uint32_t token, uint32_t nargs,
                                    target_ulong args,
-- 
2.53.0

[PATCH 2/8] target/ppc: Factor common ppc_load_epr() helper out

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/ppc/cpu.h         | 2 ++
 target/ppc/cpu.c         | 8 ++++++++
 target/ppc/excp_helper.c | 3 +--
 target/ppc/kvm.c         | 2 +-
 4 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index d637a50798f..e3e4bce91b7 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2822,6 +2822,8 @@ enum {
 target_ulong cpu_read_xer(const CPUPPCState *env);
 void cpu_write_xer(CPUPPCState *env, target_ulong xer);
 
+uint64_t ppc_load_epr(CPUPPCState *env);
+
 /*
  * All 64-bit server processors compliant with arch 2.x, ie. 970 and newer,
  * have PPC_SEGMENT_64B.
diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
index 4d8faaddee2..f24801a9731 100644
--- a/target/ppc/cpu.c
+++ b/target/ppc/cpu.c
@@ -26,6 +26,7 @@
 #include "fpu/softfloat-helpers.h"
 #include "mmu-hash64.h"
 #include "helper_regs.h"
+#include "system/memory.h"
 #include "system/tcg.h"
 
 target_ulong cpu_read_xer(const CPUPPCState *env)
@@ -105,6 +106,13 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
     ppc_maybe_interrupt(env);
 }
 
+uint64_t ppc_load_epr(CPUPPCState *env)
+{
+    CPUState *cs = env_cpu(env);
+
+    return ldl_phys(cs->as, env->mpic_iack);
+}
+
 #if defined(TARGET_PPC64)
 void ppc_update_ciabr(CPUPPCState *env)
 {
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 6d05b865058..3b476c145ab 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1166,9 +1166,8 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
         break;
     case POWERPC_EXCP_EXTERNAL:  /* External input                           */
         if (env->mpic_proxy) {
-            CPUState *cs = env_cpu(env);
             /* IACK the IRQ on delivery */
-            env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
+            env->spr[SPR_BOOKE_EPR] = ppc_load_epr(env);
         }
         break;
     case POWERPC_EXCP_ALIGN:     /* Alignment exception                      */
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 41bd03ec2a2..3bff75b7f54 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -1692,7 +1692,7 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 #endif
     case KVM_EXIT_EPR:
         trace_kvm_handle_epr();
-        run->epr.epr = ldl_phys(cs->as, env->mpic_iack);
+        run->epr.epr = ppc_load_epr(env);
         ret = 0;
         break;
     case KVM_EXIT_WATCHDOG:
-- 
2.53.0

[PATCH 3/8] target/ppc/mmu: Remove unused hash32_store_hpte() helpers

[Philippe Mathieu-Daudé]

The hash32_store_hpte() helpers are unused since commit
6e8a65abbbd ("ppc/hash32: Rework R and C bit updates"),
7 years ago. Remove them.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/ppc/mmu-hash32.h | 16 ----------------
 1 file changed, 16 deletions(-)

diff --git a/target/ppc/mmu-hash32.h b/target/ppc/mmu-hash32.h
index 04c23ea75ed..5705f57935b 100644
--- a/target/ppc/mmu-hash32.h
+++ b/target/ppc/mmu-hash32.h
@@ -87,22 +87,6 @@ static inline target_ulong ppc_hash32_load_hpte1(PowerPCCPU *cpu,
     return ldl_phys(CPU(cpu)->as, base + pte_offset + HASH_PTE_SIZE_32 / 2);
 }
 
-static inline void ppc_hash32_store_hpte0(PowerPCCPU *cpu,
-                                          hwaddr pte_offset, target_ulong pte0)
-{
-    target_ulong base = ppc_hash32_hpt_base(cpu);
-
-    stl_phys(CPU(cpu)->as, base + pte_offset, pte0);
-}
-
-static inline void ppc_hash32_store_hpte1(PowerPCCPU *cpu,
-                                          hwaddr pte_offset, target_ulong pte1)
-{
-    target_ulong base = ppc_hash32_hpt_base(cpu);
-
-    stl_phys(CPU(cpu)->as, base + pte_offset + HASH_PTE_SIZE_32 / 2, pte1);
-}
-
 static inline hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash)
 {
     return (hash * HASH_PTEG_SIZE_32) & ppc_hash32_hpt_mask(cpu);
-- 
2.53.0

[PATCH 4/8] target/ppc/mmu: Restrict hash32_load_hpte() helpers scope

[Philippe Mathieu-Daudé]

hash32_load_hpte() helpers are only used within mmu-hash32.c,
no need to have each file including "mmu-hash32.h" to compile
them. Move their definition to this source file.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/ppc/mmu-hash32.h | 16 ----------------
 target/ppc/mmu-hash32.c | 14 ++++++++++++++
 2 files changed, 14 insertions(+), 16 deletions(-)

diff --git a/target/ppc/mmu-hash32.h b/target/ppc/mmu-hash32.h
index 5705f57935b..bfea03ea872 100644
--- a/target/ppc/mmu-hash32.h
+++ b/target/ppc/mmu-hash32.h
@@ -71,22 +71,6 @@ static inline hwaddr ppc_hash32_hpt_mask(PowerPCCPU *cpu)
     return ((cpu->env.spr[SPR_SDR1] & SDR_32_HTABMASK) << 16) | 0xFFFF;
 }
 
-static inline target_ulong ppc_hash32_load_hpte0(PowerPCCPU *cpu,
-                                                 hwaddr pte_offset)
-{
-    target_ulong base = ppc_hash32_hpt_base(cpu);
-
-    return ldl_phys(CPU(cpu)->as, base + pte_offset);
-}
-
-static inline target_ulong ppc_hash32_load_hpte1(PowerPCCPU *cpu,
-                                                 hwaddr pte_offset)
-{
-    target_ulong base = ppc_hash32_hpt_base(cpu);
-
-    return ldl_phys(CPU(cpu)->as, base + pte_offset + HASH_PTE_SIZE_32 / 2);
-}
-
 static inline hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash)
 {
     return (hash * HASH_PTEG_SIZE_32) & ppc_hash32_hpt_mask(cpu);
diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c
index 8b980a5aa90..08c9f63a132 100644
--- a/target/ppc/mmu-hash32.c
+++ b/target/ppc/mmu-hash32.c
@@ -201,6 +201,20 @@ static bool ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr,
     return false;
 }
 
+static target_ulong ppc_hash32_load_hpte0(PowerPCCPU *cpu, hwaddr pte_offset)
+{
+    target_ulong base = ppc_hash32_hpt_base(cpu);
+
+    return ldl_phys(CPU(cpu)->as, base + pte_offset);
+}
+
+static target_ulong ppc_hash32_load_hpte1(PowerPCCPU *cpu, hwaddr pte_offset)
+{
+    target_ulong base = ppc_hash32_hpt_base(cpu);
+
+    return ldl_phys(CPU(cpu)->as, base + pte_offset + HASH_PTE_SIZE_32 / 2);
+}
+
 static hwaddr ppc_hash32_pteg_search(PowerPCCPU *cpu, hwaddr pteg_off,
                                      bool secondary, target_ulong ptem,
                                      ppc_hash_pte32_t *pte)
-- 
2.53.0

[PATCH 5/8] target/ppc/mmu: Replace legacy ld/st_phys() -> address_space_ld/st()

[Philippe Mathieu-Daudé]

Prefer the address_space_ld/st API over the legacy ld_phys()
because it allow checking for bus access fault.

This code however doesn't check for fault, so we simply inline
the calls (not specifying any memory transaction attribute nor
expecting transation result) per the definition in
"system/memory_ldst_phys_endian.h.inc":

 27 static inline uint32_t LD_PHYS(l)(ARG1_DECL, hwaddr addr)
 28 {
 29     return ADDRESS_SPACE_LD(l)(ARG1, addr, MEMTXATTRS_UNSPECIFIED, NULL);
 30 }

 28 static inline void glue(stb_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint8_t val)
 29 {
 30     glue(address_space_stb, SUFFIX)(ARG1, addr, val,
 31                                     MEMTXATTRS_UNSPECIFIED, NULL);
 32 }

No logical change intended.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/ppc/cpu.c        |  3 ++-
 target/ppc/mmu-hash32.c | 14 ++++++++++----
 2 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
index f24801a9731..89fad5356b4 100644
--- a/target/ppc/cpu.c
+++ b/target/ppc/cpu.c
@@ -110,7 +110,8 @@ uint64_t ppc_load_epr(CPUPPCState *env)
 {
     CPUState *cs = env_cpu(env);
 
-    return ldl_phys(cs->as, env->mpic_iack);
+    return address_space_ldl(cs->as, env->mpic_iack,
+                             MEMTXATTRS_UNSPECIFIED, NULL);
 }
 
 #if defined(TARGET_PPC64)
diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c
index 08c9f63a132..81fa7336b76 100644
--- a/target/ppc/mmu-hash32.c
+++ b/target/ppc/mmu-hash32.c
@@ -23,6 +23,7 @@
 #include "exec/page-protection.h"
 #include "exec/target_page.h"
 #include "system/kvm.h"
+#include "system/memory.h"
 #include "kvm_ppc.h"
 #include "internal.h"
 #include "mmu-hash32.h"
@@ -205,14 +206,17 @@ static target_ulong ppc_hash32_load_hpte0(PowerPCCPU *cpu, hwaddr pte_offset)
 {
     target_ulong base = ppc_hash32_hpt_base(cpu);
 
-    return ldl_phys(CPU(cpu)->as, base + pte_offset);
+    return address_space_ldl(CPU(cpu)->as, base + pte_offset,
+                             MEMTXATTRS_UNSPECIFIED, NULL);
 }
 
 static target_ulong ppc_hash32_load_hpte1(PowerPCCPU *cpu, hwaddr pte_offset)
 {
     target_ulong base = ppc_hash32_hpt_base(cpu);
 
-    return ldl_phys(CPU(cpu)->as, base + pte_offset + HASH_PTE_SIZE_32 / 2);
+    return address_space_ldl(CPU(cpu)->as,
+                             base + pte_offset + HASH_PTE_SIZE_32 / 2,
+                             MEMTXATTRS_UNSPECIFIED, NULL);
 }
 
 static hwaddr ppc_hash32_pteg_search(PowerPCCPU *cpu, hwaddr pteg_off,
@@ -253,7 +257,8 @@ static void ppc_hash32_set_r(PowerPCCPU *cpu, hwaddr pte_offset, uint32_t pte1)
     hwaddr offset = pte_offset + 6;
 
     /* The HW performs a non-atomic byte update */
-    stb_phys(CPU(cpu)->as, base + offset, ((pte1 >> 8) & 0xff) | 0x01);
+    address_space_stb(CPU(cpu)->as, base + offset, ((pte1 >> 8) & 0xff) | 0x01,
+                      MEMTXATTRS_UNSPECIFIED, NULL);
 }
 
 static void ppc_hash32_set_c(PowerPCCPU *cpu, hwaddr pte_offset, uint64_t pte1)
@@ -262,7 +267,8 @@ static void ppc_hash32_set_c(PowerPCCPU *cpu, hwaddr pte_offset, uint64_t pte1)
     hwaddr offset = pte_offset + 7;
 
     /* The HW performs a non-atomic byte update */
-    stb_phys(CPU(cpu)->as, base + offset, (pte1 & 0xff) | 0x80);
+    address_space_stb(CPU(cpu)->as, base + offset, (pte1 & 0xff) | 0x80,
+                      MEMTXATTRS_UNSPECIFIED, NULL);
 }
 
 static hwaddr ppc_hash32_htab_lookup(PowerPCCPU *cpu,
-- 
2.53.0

[PATCH 6/8] hw/ppc/pegasos: Introduce rtas_ldl() / rtas_stl() helpers

[Philippe Mathieu-Daudé]

In preparation of replacing the ldl_be_phys() and stl_be_phys()
legacy calls in the next commit, introduce the rtas_ldl() and
rtas_stl() helpers.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/ppc/pegasos.c | 66 ++++++++++++++++++++++++++++--------------------
 1 file changed, 38 insertions(+), 28 deletions(-)

diff --git a/hw/ppc/pegasos.c b/hw/ppc/pegasos.c
index ac9fc5a6542..4217af25807 100644
--- a/hw/ppc/pegasos.c
+++ b/hw/ppc/pegasos.c
@@ -591,13 +591,23 @@ enum pegasos2_rtas_tokens {
     RTAS_SYSTEM_REBOOT = 20,
 };
 
+static uint32_t rtas_ldl(AddressSpace *as, hwaddr addr)
+{
+    return ldl_be_phys(as, addr);
+}
+
+static void rtas_stl(AddressSpace *as, hwaddr addr, uint32_t value)
+{
+    stl_be_phys(as, addr, value);
+}
+
 static target_ulong pegasos2_rtas(PowerPCCPU *cpu, PegasosMachineState *pm,
                                   target_ulong args_real)
 {
     AddressSpace *as = CPU(cpu)->as;
-    uint32_t token = ldl_be_phys(as, args_real);
-    uint32_t nargs = ldl_be_phys(as, args_real + 4);
-    uint32_t nrets = ldl_be_phys(as, args_real + 8);
+    uint32_t token = rtas_ldl(as, args_real);
+    uint32_t nargs = rtas_ldl(as, args_real + 4);
+    uint32_t nrets = rtas_ldl(as, args_real + 8);
     uint32_t args = args_real + 12;
     uint32_t rets = args_real + 12 + nargs * 4;
 
@@ -613,19 +623,19 @@ static target_ulong pegasos2_rtas(PowerPCCPU *cpu, PegasosMachineState *pm,
         QDict *qd = qobject_to(QDict, qo);
 
         if (nargs != 0 || nrets != 8 || !qd) {
-            stl_be_phys(as, rets, -1);
+            rtas_stl(as, rets, -1);
             qobject_unref(qo);
             return H_PARAMETER;
         }
 
-        stl_be_phys(as, rets, 0);
-        stl_be_phys(as, rets + 4, qdict_get_int(qd, "tm_year") + 1900);
-        stl_be_phys(as, rets + 8, qdict_get_int(qd, "tm_mon") + 1);
-        stl_be_phys(as, rets + 12, qdict_get_int(qd, "tm_mday"));
-        stl_be_phys(as, rets + 16, qdict_get_int(qd, "tm_hour"));
-        stl_be_phys(as, rets + 20, qdict_get_int(qd, "tm_min"));
-        stl_be_phys(as, rets + 24, qdict_get_int(qd, "tm_sec"));
-        stl_be_phys(as, rets + 28, 0);
+        rtas_stl(as, rets, 0);
+        rtas_stl(as, rets + 4, qdict_get_int(qd, "tm_year") + 1900);
+        rtas_stl(as, rets + 8, qdict_get_int(qd, "tm_mon") + 1);
+        rtas_stl(as, rets + 12, qdict_get_int(qd, "tm_mday"));
+        rtas_stl(as, rets + 16, qdict_get_int(qd, "tm_hour"));
+        rtas_stl(as, rets + 20, qdict_get_int(qd, "tm_min"));
+        rtas_stl(as, rets + 24, qdict_get_int(qd, "tm_sec"));
+        rtas_stl(as, rets + 28, 0);
         qobject_unref(qo);
         return H_SUCCESS;
     }
@@ -634,15 +644,15 @@ static target_ulong pegasos2_rtas(PowerPCCPU *cpu, PegasosMachineState *pm,
         uint32_t addr, len, val;
 
         if (nargs != 2 || nrets != 2) {
-            stl_be_phys(as, rets, -1);
+            rtas_stl(as, rets, -1);
             return H_PARAMETER;
         }
-        addr = ldl_be_phys(as, args);
-        len = ldl_be_phys(as, args + 4);
+        addr = rtas_ldl(as, args);
+        len = rtas_ldl(as, args + 4);
         val = pegasos2_pci_config_read(pm, !(addr >> 24),
                                        addr & 0x0fffffff, len);
-        stl_be_phys(as, rets, 0);
-        stl_be_phys(as, rets + 4, val);
+        rtas_stl(as, rets, 0);
+        rtas_stl(as, rets + 4, val);
         return H_SUCCESS;
     }
     case RTAS_WRITE_PCI_CONFIG:
@@ -650,39 +660,39 @@ static target_ulong pegasos2_rtas(PowerPCCPU *cpu, PegasosMachineState *pm,
         uint32_t addr, len, val;
 
         if (nargs != 3 || nrets != 1) {
-            stl_be_phys(as, rets, -1);
+            rtas_stl(as, rets, -1);
             return H_PARAMETER;
         }
-        addr = ldl_be_phys(as, args);
-        len = ldl_be_phys(as, args + 4);
-        val = ldl_be_phys(as, args + 8);
+        addr = rtas_ldl(as, args);
+        len = rtas_ldl(as, args + 4);
+        val = rtas_ldl(as, args + 8);
         pegasos2_pci_config_write(pm, !(addr >> 24),
                                   addr & 0x0fffffff, len, val);
-        stl_be_phys(as, rets, 0);
+        rtas_stl(as, rets, 0);
         return H_SUCCESS;
     }
     case RTAS_DISPLAY_CHARACTER:
         if (nargs != 1 || nrets != 1) {
-            stl_be_phys(as, rets, -1);
+            rtas_stl(as, rets, -1);
             return H_PARAMETER;
         }
-        qemu_log_mask(LOG_UNIMP, "%c", ldl_be_phys(as, args));
-        stl_be_phys(as, rets, 0);
+        qemu_log_mask(LOG_UNIMP, "%c", rtas_ldl(as, args));
+        rtas_stl(as, rets, 0);
         return H_SUCCESS;
     case RTAS_POWER_OFF:
     {
         if (nargs != 2 || nrets != 1) {
-            stl_be_phys(as, rets, -1);
+            rtas_stl(as, rets, -1);
             return H_PARAMETER;
         }
         qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
-        stl_be_phys(as, rets, 0);
+        rtas_stl(as, rets, 0);
         return H_SUCCESS;
     }
     default:
         qemu_log_mask(LOG_UNIMP, "Unknown RTAS token %u (args=%u, rets=%u)\n",
                       token, nargs, nrets);
-        stl_be_phys(as, rets, 0);
+        rtas_stl(as, rets, 0);
         return H_SUCCESS;
     }
 }
-- 
2.53.0

[PATCH 7/8] hw/ppc/pegasos: Replace legacy ld/st_phys() -> address_space_ld/st()

[Philippe Mathieu-Daudé]

Prefer the address_space_ld/st API over the legacy ld_phys()
because it allow checking for bus access fault.

This code however doesn't check for fault, so we simply inline
the calls (not specifying any memory transaction attribute nor
expecting transation result) per the definition in
"system/memory_ldst_phys_endian.h.inc":

 27 static inline uint32_t LD_PHYS(l)(ARG1_DECL, hwaddr addr)
 28 {
 29     return ADDRESS_SPACE_LD(l)(ARG1, addr, MEMTXATTRS_UNSPECIFIED, NULL);
 30 }

 42 static inline void ST_PHYS(l)(ARG1_DECL, hwaddr addr, uint32_t val)
 43 {
 44     ADDRESS_SPACE_ST(l)(ARG1, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
 45 }

No logical change intended.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/ppc/pegasos.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/ppc/pegasos.c b/hw/ppc/pegasos.c
index 4217af25807..52e35949cc1 100644
--- a/hw/ppc/pegasos.c
+++ b/hw/ppc/pegasos.c
@@ -21,6 +21,7 @@
 #include "hw/ide/pci.h"
 #include "hw/i2c/smbus_eeprom.h"
 #include "hw/core/qdev-properties.h"
+#include "system/memory.h"
 #include "system/reset.h"
 #include "system/runstate.h"
 #include "system/qtest.h"
@@ -593,12 +594,12 @@ enum pegasos2_rtas_tokens {
 
 static uint32_t rtas_ldl(AddressSpace *as, hwaddr addr)
 {
-    return ldl_be_phys(as, addr);
+    return address_space_ldl(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
 }
 
 static void rtas_stl(AddressSpace *as, hwaddr addr, uint32_t value)
 {
-    stl_be_phys(as, addr, value);
+    address_space_stl(as, addr, value, MEMTXATTRS_UNSPECIFIED, NULL);
 }
 
 static target_ulong pegasos2_rtas(PowerPCCPU *cpu, PegasosMachineState *pm,
-- 
2.53.0

[PATCH 8/8] configs/targets: Restrict the legacy ldst_phys() API on PPC

[Philippe Mathieu-Daudé]

The 32-bit PPC target doesn't use the legacy ldst_phys() API
anymore. Set the TARGET_NOT_USING_LEGACY_LDST_PHYS_API variable
to hide the legacy API to the qemu-system-ppc binary, avoiding
further API uses to creep in.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 configs/targets/ppc-softmmu.mak | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/targets/ppc-softmmu.mak b/configs/targets/ppc-softmmu.mak
index 867898bd47c..ae7d593bf0d 100644
--- a/configs/targets/ppc-softmmu.mak
+++ b/configs/targets/ppc-softmmu.mak
@@ -3,3 +3,4 @@ TARGET_BIG_ENDIAN=y
 TARGET_KVM_HAVE_GUEST_DEBUG=y
 TARGET_XML_FILES= power-core.xml power-fpu.xml power-altivec.xml power-spe.xml
 TARGET_LONG_BITS=32
+TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y
-- 
2.53.0

Re: [PATCH 5/8] target/ppc/mmu: Replace legacy ld/st_phys() -> address_space_ld/st()

[BALATON Zoltan]

[-- Attachment #1: Type: text/plain, Size: 855 bytes --]

On Thu, 19 Mar 2026, Philippe Mathieu-Daudé wrote:
> Prefer the address_space_ld/st API over the legacy ld_phys()
> because it allow checking for bus access fault.
>
> This code however doesn't check for fault, so we simply inline
> the calls (not specifying any memory transaction attribute nor
> expecting transation result) per the definition in
> "system/memory_ldst_phys_endian.h.inc":

Recently when trying to remove _nomigrate memory region functions I was 
told if some convenience function has more than 1 use it's probably worth 
to keep it. This looks like similar case even more so as the replacement 
is unnecessarily more complicated. So what's the problem with ld_phys in 
the first place and why do you want to replace it with a less convenient 
function? If there's a reason maybe say that in the commit message.

Regards,
BALATON Zoltan