From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-riscv@nongnu.org
Cc: Nicholas Piggin <npiggin@gmail.com>,
Laurent Vivier <laurent@vivier.eu>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
qemu-devel@nongnu.org, Joel Stanley <joel@jms.id.au>
Subject: [PATCH v3 0/3] target/riscv: corner case fixes
Date: Sun, 22 Mar 2026 00:45:51 +1000 [thread overview]
Message-ID: <20260321144554.606417-1-npiggin@gmail.com> (raw)
Changes:
v3:
* Added vloxei8.v to overflow test.
* Added store variants of interrupted vector ops tests.
v2:
* Added a tcg tests build-time check for vector intrinsics support
in target compiler before building new tests that require it.
ci images may not support these yet unfortunately, but upgrading
those will be a separate effort.
Thanks,
Nick
Nicholas Piggin (3):
target/riscv: Fix IALIGN check in misa write
target/riscv: Fix vector whole ldst vstart check
tests/tcg: Add riscv test for interrupted vector ops
target/riscv/csr.c | 16 +-
target/riscv/vector_helper.c | 2 +
tests/tcg/riscv64/Makefile.softmmu-target | 5 +
tests/tcg/riscv64/Makefile.target | 16 ++
tests/tcg/riscv64/misa-ialign.S | 88 ++++++
tests/tcg/riscv64/test-interrupted-v.c | 329 ++++++++++++++++++++++
tests/tcg/riscv64/test-vstart-overflow.c | 78 +++++
7 files changed, 531 insertions(+), 3 deletions(-)
create mode 100644 tests/tcg/riscv64/misa-ialign.S
create mode 100644 tests/tcg/riscv64/test-interrupted-v.c
create mode 100644 tests/tcg/riscv64/test-vstart-overflow.c
--
2.51.0
next reply other threads:[~2026-03-21 14:47 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-21 14:45 Nicholas Piggin [this message]
2026-03-21 14:45 ` [PATCH v3 1/3] target/riscv: Fix IALIGN check in misa write Nicholas Piggin
2026-03-25 1:35 ` Alistair Francis
2026-03-25 3:08 ` Chao Liu
2026-03-25 3:26 ` Alistair Francis
2026-03-25 3:40 ` Chao Liu
2026-03-26 6:29 ` Nicholas Piggin
2026-03-21 14:45 ` [PATCH v3 2/3] target/riscv: Fix vector whole ldst vstart check Nicholas Piggin
2026-03-25 1:57 ` Alistair Francis
2026-03-25 2:10 ` Chao Liu
2026-03-21 14:45 ` [PATCH v3 3/3] tests/tcg: Add riscv test for interrupted vector ops Nicholas Piggin
2026-03-25 2:08 ` Alistair Francis
2026-03-25 3:19 ` Chao Liu
2026-03-26 6:32 ` Nicholas Piggin
2026-03-25 2:20 ` [PATCH v3 0/3] target/riscv: corner case fixes Alistair Francis
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