* [PATCH] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI
@ 2026-03-24 5:26 Jay Chang
2026-03-24 9:48 ` Nutty.Liu
0 siblings, 1 reply; 2+ messages in thread
From: Jay Chang @ 2026-03-24 5:26 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Jay Chang,
Frank Chang
Replace the temporary custom extension bit (TC[32]) with the
standard EN_PRI bit defined in RISC-V IOMMU specification.
Signed-off-by: Jay Chang <jay.chang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
hw/riscv/riscv-iommu.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index 225394ea83..7d5c8cd7f5 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -1572,11 +1572,8 @@ static int riscv_iommu_translate(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
riscv_iommu_hpm_incr_ctr(s, ctx, RISCV_IOMMU_HPMEVENT_URQ);
iot_cache = g_hash_table_ref(s->iot_cache);
- /*
- * TC[32] is reserved for custom extensions, used here to temporarily
- * enable automatic page-request generation for ATS queries.
- */
- enable_pri = (iotlb->perm == IOMMU_NONE) && (ctx->tc & BIT_ULL(32));
+ enable_pri = (iotlb->perm == IOMMU_NONE) &&
+ (ctx->tc & RISCV_IOMMU_DC_TC_EN_PRI);
enable_pid = (ctx->tc & RISCV_IOMMU_DC_TC_PDTV);
/* Check for ATS request. */
--
2.48.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI
2026-03-24 5:26 [PATCH] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI Jay Chang
@ 2026-03-24 9:48 ` Nutty.Liu
0 siblings, 0 replies; 2+ messages in thread
From: Nutty.Liu @ 2026-03-24 9:48 UTC (permalink / raw)
To: Jay Chang, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Frank Chang
On 3/24/2026 1:26 PM, Jay Chang wrote:
> Replace the temporary custom extension bit (TC[32]) with the
> standard EN_PRI bit defined in RISC-V IOMMU specification.
>
> Signed-off-by: Jay Chang <jay.chang@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
> hw/riscv/riscv-iommu.c | 7 ++-----
> 1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index 225394ea83..7d5c8cd7f5 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -1572,11 +1572,8 @@ static int riscv_iommu_translate(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
> riscv_iommu_hpm_incr_ctr(s, ctx, RISCV_IOMMU_HPMEVENT_URQ);
>
> iot_cache = g_hash_table_ref(s->iot_cache);
> - /*
> - * TC[32] is reserved for custom extensions, used here to temporarily
> - * enable automatic page-request generation for ATS queries.
> - */
> - enable_pri = (iotlb->perm == IOMMU_NONE) && (ctx->tc & BIT_ULL(32));
> + enable_pri = (iotlb->perm == IOMMU_NONE) &&
> + (ctx->tc & RISCV_IOMMU_DC_TC_EN_PRI);
Better to align with the first word on the right side of '='. Like:
+ enable_pri = (iotlb->perm == IOMMU_NONE) &&
+ (ctx->tc & RISCV_IOMMU_DC_TC_EN_PRI);
Otherwise,
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Thanks,
Nutty
> enable_pid = (ctx->tc & RISCV_IOMMU_DC_TC_PDTV);
>
> /* Check for ATS request. */
^ permalink raw reply [flat|nested] 2+ messages in thread
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