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From: Jay Chang <jay.chang@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Weiwei Li <liwei1518@gmail.com>,
	Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,
	Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
	Chao Liu <chao.liu.zevorn@gmail.com>,
	Jay Chang <jay.chang@sifive.com>,
	Frank Chang <frank.chang@sifive.com>
Subject: [PATCH v2 1/2] hw/riscv/riscv-iommu-hpm: Fix irq_overflow_left residual value bug
Date: Wed, 25 Mar 2026 13:00:10 +0800	[thread overview]
Message-ID: <20260325050011.66722-2-jay.chang@sifive.com> (raw)
In-Reply-To: <20260325050011.66722-1-jay.chang@sifive.com>

Reset irq_overflow_left to 0 before setting up a new timer. Without
this fix, a stale irq_overflow_left value from a previous timer setup
could cause incorrect timer behavior.

Signed-off-by: Jay Chang <jay.chang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
---
 hw/riscv/riscv-iommu-hpm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/riscv/riscv-iommu-hpm.c b/hw/riscv/riscv-iommu-hpm.c
index c5034bff79..e8d284ac8b 100644
--- a/hw/riscv/riscv-iommu-hpm.c
+++ b/hw/riscv/riscv-iommu-hpm.c
@@ -228,6 +228,7 @@ static void hpm_setup_timer(RISCVIOMMUState *s, uint64_t value)
     }
 
     overflow_at = (uint64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + overflow_ns;
+    s->irq_overflow_left = 0;
 
     if (overflow_at > INT64_MAX) {
         s->irq_overflow_left = overflow_at - INT64_MAX;
-- 
2.48.1



  reply	other threads:[~2026-03-25  5:00 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-25  5:00 [PATCH v2 0/2] Bug fixes and IPSR.PMIP support Jay Chang
2026-03-25  5:00 ` Jay Chang [this message]
2026-03-25  5:00 ` [PATCH v2 2/2] hw/riscv/riscv-iommu: Add IPSR.PMIP RW1C support Jay Chang

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