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Wed, 25 Mar 2026 09:45:16 -0700 (PDT) X-Received: by 2002:a05:600c:4f48:b0:485:3d00:efd with SMTP id 5b1f17b1804b1-48715fbfc42mr67523955e9.7.1774457115522; Wed, 25 Mar 2026 09:45:15 -0700 (PDT) Received: from [192.168.10.48] ([151.49.85.67]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b9192e3f9sm1200821f8f.7.2026.03.25.09.45.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Mar 2026 09:45:12 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Mohamed Mediouni Subject: [PULL 11/19] target/i386: emulate: indirect access to CRs Date: Wed, 25 Mar 2026 17:44:45 +0100 Message-ID: <20260325164453.72127-12-pbonzini@redhat.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260325164453.72127-1-pbonzini@redhat.com> References: <20260325164453.72127-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mohamed Mediouni Prepare to have on-demand fetch of registers from the backend during faults. For x86_64 macOS, copy the function there too. Signed-off-by: Mohamed Mediouni Link: https://lore.kernel.org/r/20260324151323.74473-9-mohamed@unpredictable.fr Signed-off-by: Paolo Bonzini --- target/i386/emulate/x86_emu.h | 3 +++ target/i386/emulate/x86_helpers.c | 27 ++++++++++++++++----------- target/i386/emulate/x86_mmu.c | 8 ++------ target/i386/hvf/x86.c | 11 +++++++++++ 4 files changed, 32 insertions(+), 17 deletions(-) diff --git a/target/i386/emulate/x86_emu.h b/target/i386/emulate/x86_emu.h index 4ed970bd536..a8d4c93098d 100644 --- a/target/i386/emulate/x86_emu.h +++ b/target/i386/emulate/x86_emu.h @@ -28,6 +28,7 @@ struct x86_emul_ops { MMUTranslateResult (*mmu_gva_to_gpa) (CPUState *cpu, target_ulong gva, uint64_t *gpa, MMUTranslateFlags flags); void (*read_segment_descriptor)(CPUState *cpu, struct x86_segment_descriptor *desc, enum X86Seg seg); + target_ulong (*read_cr) (CPUState *cpu, int cr); void (*handle_io)(CPUState *cpu, uint16_t port, void *data, int direction, int size, int count); void (*simulate_rdmsr)(CPUState *cs); @@ -45,6 +46,8 @@ void x86_emul_raise_exception(CPUX86State *env, int exception_index, int error_c target_ulong read_reg(CPUX86State *env, int reg, int size); void write_reg(CPUX86State *env, int reg, target_ulong val, int size); +target_ulong x86_read_cr(CPUState *cpu, int cr); + target_ulong read_val_from_reg(void *reg_ptr, int size); void write_val_to_reg(void *reg_ptr, target_ulong val, int size); bool write_val_ext(CPUX86State *env, struct x86_decode_op *decode, target_ulong val, int size); diff --git a/target/i386/emulate/x86_helpers.c b/target/i386/emulate/x86_helpers.c index ebbf40f2b05..c817015ef92 100644 --- a/target/i386/emulate/x86_helpers.c +++ b/target/i386/emulate/x86_helpers.c @@ -206,15 +206,26 @@ bool x86_read_call_gate(CPUState *cpu, struct x86_call_gate *idt_desc, return true; } -bool x86_is_protected(CPUState *cpu) +target_ulong x86_read_cr(CPUState *cpu, int cr) { X86CPU *x86_cpu = X86_CPU(cpu); CPUX86State *env = &x86_cpu->env; - uint64_t cr0 = env->cr[0]; + + if (emul_ops->read_cr) { + return emul_ops->read_cr(cpu, cr); + } + return env->cr[cr]; +} + +bool x86_is_protected(CPUState *cpu) +{ + uint64_t cr0; + if (emul_ops->is_protected_mode) { return emul_ops->is_protected_mode(cpu); } + cr0 = x86_read_cr(cpu, 0); return cr0 & CR0_PE_MASK; } @@ -245,9 +256,7 @@ bool x86_is_long_mode(CPUState *cpu) bool x86_is_la57(CPUState *cpu) { - X86CPU *x86_cpu = X86_CPU(cpu); - CPUX86State *env = &x86_cpu->env; - uint64_t is_la57 = env->cr[4] & CR4_LA57_MASK; + uint64_t is_la57 = x86_read_cr(cpu, 4) & CR4_LA57_MASK; return is_la57; } @@ -259,18 +268,14 @@ bool x86_is_long64_mode(CPUState *cpu) bool x86_is_paging_mode(CPUState *cpu) { - X86CPU *x86_cpu = X86_CPU(cpu); - CPUX86State *env = &x86_cpu->env; - uint64_t cr0 = env->cr[0]; + uint64_t cr0 = x86_read_cr(cpu, 0); return cr0 & CR0_PG_MASK; } bool x86_is_pae_enabled(CPUState *cpu) { - X86CPU *x86_cpu = X86_CPU(cpu); - CPUX86State *env = &x86_cpu->env; - uint64_t cr4 = env->cr[4]; + uint64_t cr4 = x86_read_cr(cpu, 4); return cr4 & CR4_PAE_MASK; } diff --git a/target/i386/emulate/x86_mmu.c b/target/i386/emulate/x86_mmu.c index 670939acdba..ba0ebe4268d 100644 --- a/target/i386/emulate/x86_mmu.c +++ b/target/i386/emulate/x86_mmu.c @@ -114,8 +114,6 @@ static bool get_pt_entry(CPUState *cpu, struct gpt_translation *pt, static MMUTranslateResult test_pt_entry(CPUState *cpu, struct gpt_translation *pt, int level, int *largeness, bool pae, MMUTranslateFlags flags) { - X86CPU *x86_cpu = X86_CPU(cpu); - CPUX86State *env = &x86_cpu->env; uint64_t pte = pt->pte[level]; if (!pte_present(pte)) { @@ -130,7 +128,7 @@ static MMUTranslateResult test_pt_entry(CPUState *cpu, struct gpt_translation *p *largeness = level; } - uint32_t cr0 = env->cr[0]; + uint32_t cr0 = x86_read_cr(cpu, 0); /* check protection */ if (cr0 & CR0_WP_MASK) { if (mmu_validate_write(flags) && !pte_write_access(pte)) { @@ -184,11 +182,9 @@ static inline uint64_t large_page_gpa(struct gpt_translation *pt, bool pae, static MMUTranslateResult walk_gpt(CPUState *cpu, target_ulong addr, MMUTranslateFlags flags, struct gpt_translation *pt, bool pae) { - X86CPU *x86_cpu = X86_CPU(cpu); - CPUX86State *env = &x86_cpu->env; int top_level, level; int largeness = 0; - target_ulong cr3 = env->cr[3]; + target_ulong cr3 = x86_read_cr(cpu, 3); uint64_t page_mask = pae ? PAE_PTE_PAGE_MASK : LEGACY_PTE_PAGE_MASK; MMUTranslateResult res; diff --git a/target/i386/hvf/x86.c b/target/i386/hvf/x86.c index 7fe710aca3b..bae2f30fa28 100644 --- a/target/i386/hvf/x86.c +++ b/target/i386/hvf/x86.c @@ -143,6 +143,17 @@ bool x86_is_la57(CPUState *cpu) return false; } +target_ulong x86_read_cr(CPUState *cpu, int cr) +{ + X86CPU *x86_cpu = X86_CPU(cpu); + CPUX86State *env = &x86_cpu->env; + + if (emul_ops->read_cr) { + return emul_ops->read_cr(cpu, cr); + } + return env->cr[cr]; +} + bool x86_is_long64_mode(CPUState *cpu) { struct vmx_segment desc; -- 2.53.0