From: Alireza Sanaee via qemu development <qemu-devel@nongnu.org>
To: <qemu-devel@nongnu.org>
Cc: <anisa.su@samsung.com>, <armbru@redhat.com>,
<berrange@redhat.com>, <eblake@redhat.com>,
<jonathan.cameron@huawei.com>, <linux-cxl@vger.kernel.org>,
<linuxarm@huawei.com>, <lizhijian@fujitsu.com>, <mst@redhat.com>,
<pbonzini@redhat.com>, <gourry@gourry.net>, <nifan.cxl@gmail.com>,
<me@linux.beauty>
Subject: [PATCH 4/9] hw/cxl: Carry backend metadata in DC extent records
Date: Wed, 25 Mar 2026 18:42:52 +0000 [thread overview]
Message-ID: <20260325184259.366-5-alireza.sanaee@huawei.com> (raw)
In-Reply-To: <20260325184259.366-1-alireza.sanaee@huawei.com>
The lazy dc-regions-total-size flow needs more than DPA and length for each
pending or committed extent. Later stages need to remember which backend
was selected for the extent, which fixed window owns the mapping, and which
region/offset the request came from.
Extend CXLDCExtent and the helper APIs so add, copy, and release paths can
carry that metadata alongside the range information. This is preparatory
plumbing for the patches that map accepted extents into the fixed window
and tear them down on release.
Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
---
hw/cxl/cxl-mailbox-utils.c | 45 ++++++++++++++++++++++++++-----------
hw/mem/cxl_type3.c | 23 ++++++++++++++-----
include/hw/cxl/cxl_device.h | 21 +++++++++++++----
3 files changed, 67 insertions(+), 22 deletions(-)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index c83b5f90d4..c5427adb3a 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -3525,20 +3525,26 @@ CXLDCRegion *cxl_find_dc_region(CXLType3Dev *ct3d, uint64_t dpa, uint64_t len)
}
void cxl_insert_extent_to_extent_list(CXLDCExtentList *list,
+ HostMemoryBackend *hm,
+ struct CXLFixedWindow *fw,
uint64_t dpa,
uint64_t len,
uint8_t *tag,
- uint16_t shared_seq)
+ uint16_t shared_seq,
+ int rid)
{
CXLDCExtent *extent;
extent = g_new0(CXLDCExtent, 1);
+ extent->hm = hm;
+ extent->fw = fw;
extent->start_dpa = dpa;
extent->len = len;
if (tag) {
memcpy(extent->tag, tag, 0x10);
}
extent->shared_seq = shared_seq;
+ extent->rid = rid;
QTAILQ_INSERT_TAIL(list, extent, node);
}
@@ -3556,17 +3562,21 @@ void cxl_remove_extent_from_extent_list(CXLDCExtentList *list,
* Return value: the extent group where the extent is inserted.
*/
CXLDCExtentGroup *cxl_insert_extent_to_extent_group(CXLDCExtentGroup *group,
+ HostMemoryBackend *host_mem,
+ struct CXLFixedWindow *fw,
uint64_t dpa,
uint64_t len,
uint8_t *tag,
- uint16_t shared_seq)
+ uint16_t shared_seq,
+ int rid)
{
if (!group) {
group = g_new0(CXLDCExtentGroup, 1);
QTAILQ_INIT(&group->list);
}
- cxl_insert_extent_to_extent_list(&group->list, dpa, len,
- tag, shared_seq);
+ cxl_insert_extent_to_extent_list(&group->list,
+ host_mem, fw, dpa, len,
+ tag, shared_seq, rid);
return group;
}
@@ -3747,7 +3757,9 @@ static CXLRetCode cmd_dcd_add_dyn_cap_rsp(const struct cxl_cmd *cmd,
dpa = in->updated_entries[i].start_dpa;
len = in->updated_entries[i].len;
- cxl_insert_extent_to_extent_list(extent_list, dpa, len, NULL, 0);
+ cxl_insert_extent_to_extent_list(extent_list,
+ NULL, NULL, dpa, len,
+ NULL, 0, 0);
ct3d->dc.total_extent_count += 1;
ct3d->dc.nr_extents_accepted += 1;
ct3_set_region_block_backed(ct3d, dpa, len);
@@ -3774,8 +3786,11 @@ static uint32_t copy_extent_list(CXLDCExtentList *dst,
}
QTAILQ_FOREACH(ent, src, node) {
- cxl_insert_extent_to_extent_list(dst, ent->start_dpa, ent->len,
- ent->tag, ent->shared_seq);
+ cxl_insert_extent_to_extent_list(dst,
+ ent->hm, ent->fw,
+ ent->start_dpa, ent->len,
+ ent->tag, ent->shared_seq,
+ ent->rid);
cnt++;
}
return cnt;
@@ -3830,14 +3845,16 @@ static CXLRetCode cxl_dc_extent_release_dry_run(CXLType3Dev *ct3d,
if (len1) {
cxl_insert_extent_to_extent_list(updated_list,
- ent_start_dpa,
- len1, NULL, 0);
+ NULL, NULL,
+ ent_start_dpa, len1,
+ NULL, 0, ent->rid);
cnt_delta++;
}
if (len2) {
cxl_insert_extent_to_extent_list(updated_list,
- dpa + len,
- len2, NULL, 0);
+ NULL, NULL,
+ dpa + len, len2,
+ NULL, 0, ent->rid);
cnt_delta++;
}
@@ -4310,9 +4327,11 @@ static CXLRetCode cmd_fm_initiate_dc_add(const struct cxl_cmd *cmd,
for (i = 0; i < in->ext_count; i++) {
CXLDCExtentRaw *ext = &in->extents[i];
- group = cxl_insert_extent_to_extent_group(group, ext->start_dpa,
+ group = cxl_insert_extent_to_extent_group(group,
+ NULL, NULL,
+ ext->start_dpa,
ext->len, ext->tag,
- ext->shared_seq);
+ ext->shared_seq, 0);
}
cxl_extent_group_list_insert_tail(&ct3d->dc.extents_pending, group);
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 569184975f..bd32532c7a 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -2457,11 +2457,24 @@ static void qmp_cxl_process_dynamic_capacity_prescriptive(const char *path,
memcpy(extents[i].tag, &uuid.data, 0x10);
extents[i].shared_seq = 0;
if (type == DC_EVENT_ADD_CAPACITY) {
- group = cxl_insert_extent_to_extent_group(group,
- extents[i].start_dpa,
- extents[i].len,
- extents[i].tag,
- extents[i].shared_seq);
+ if (!dcd->dc.total_capacity_cmd) {
+ group = cxl_insert_extent_to_extent_group(group,
+ NULL, NULL,
+ extents[i].start_dpa,
+ extents[i].len,
+ extents[i].tag,
+ extents[i].shared_seq,
+ rid);
+ } else {
+ group = cxl_insert_extent_to_extent_group(group,
+ dcd->dc.host_dc,
+ dcd->dc.fw,
+ extents[i].start_dpa,
+ extents[i].len,
+ extents[i].tag,
+ extents[i].shared_seq,
+ rid);
+ }
}
list = list->next;
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index 630cf44e0e..a84b8ab358 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -10,6 +10,7 @@
#ifndef CXL_DEVICE_H
#define CXL_DEVICE_H
+#include "hw/cxl/cxl.h"
#include "hw/cxl/cxl_component.h"
#include "hw/pci/pci_device.h"
#include "hw/core/register.h"
@@ -643,11 +644,14 @@ typedef struct CXLDCExtentRaw {
} QEMU_PACKED CXLDCExtentRaw;
typedef struct CXLDCExtent {
+ HostMemoryBackend *hm;
+ struct CXLFixedWindow *fw;
uint64_t start_dpa;
uint64_t len;
uint8_t tag[0x10];
uint16_t shared_seq;
uint8_t rsvd[0x6];
+ int rid;
QTAILQ_ENTRY(CXLDCExtent) node;
} CXLDCExtent;
@@ -780,6 +784,7 @@ struct CXLType3Dev {
struct dynamic_capacity {
HostMemoryBackend *host_dc;
AddressSpace host_dc_as;
+ struct CXLFixedWindow *fw;
/*
* total_capacity is equivalent to the dynamic capability
* memory region size.
@@ -854,18 +859,26 @@ CXLDCRegion *cxl_find_dc_region(CXLType3Dev *ct3d, uint64_t dpa, uint64_t len);
void cxl_remove_extent_from_extent_list(CXLDCExtentList *list,
CXLDCExtent *extent);
-void cxl_insert_extent_to_extent_list(CXLDCExtentList *list, uint64_t dpa,
- uint64_t len, uint8_t *tag,
- uint16_t shared_seq);
+void cxl_insert_extent_to_extent_list(CXLDCExtentList *list,
+ HostMemoryBackend *hm,
+ struct CXLFixedWindow *fw,
+ uint64_t dpa,
+ uint64_t len,
+ uint8_t *tag,
+ uint16_t shared_seq,
+ int rid);
bool test_any_bits_set(const unsigned long *addr, unsigned long nr,
unsigned long size);
bool cxl_extents_contains_dpa_range(CXLDCExtentList *list,
uint64_t dpa, uint64_t len);
CXLDCExtentGroup *cxl_insert_extent_to_extent_group(CXLDCExtentGroup *group,
+ HostMemoryBackend *host_mem,
+ struct CXLFixedWindow *fw,
uint64_t dpa,
uint64_t len,
uint8_t *tag,
- uint16_t shared_seq);
+ uint16_t shared_seq,
+ int rid);
void cxl_extent_group_list_insert_tail(CXLDCExtentGroupList *list,
CXLDCExtentGroup *group);
uint32_t cxl_extent_group_list_delete_front(CXLDCExtentGroupList *list);
--
2.50.1 (Apple Git-155)
next prev parent reply other threads:[~2026-03-25 18:45 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-25 18:42 [QEMU PATCH 0/9] Application Specific Tagged Memory Support in CXL Type 3 Devices Alireza Sanaee via qemu development
2026-03-25 18:42 ` [PATCH 1/9] hw/mem: Add tag support to generic host memory backends Alireza Sanaee via qemu development
2026-03-26 10:42 ` Markus Armbruster
2026-03-26 11:29 ` Alireza Sanaee via qemu development
2026-03-26 13:01 ` Markus Armbruster
2026-03-26 13:04 ` Alireza Sanaee via qemu development
2026-03-25 18:42 ` [PATCH 2/9] hw/cxl: Allow initializing type3 device with no backing device Alireza Sanaee via qemu development
2026-03-25 18:42 ` [PATCH 3/9] hw/cxl: Hook up tagged host memory backends at runtime for DC extents Alireza Sanaee via qemu development
2026-03-25 18:42 ` Alireza Sanaee via qemu development [this message]
2026-03-25 18:42 ` [PATCH 5/9] hw/cxl: Map lazy memory backend after host acceptance Alireza Sanaee via qemu development
2026-03-25 18:42 ` [PATCH 6/9] hw/cxl: Create direct fixed-window aliases for accepted extents Alireza Sanaee via qemu development
2026-03-25 18:42 ` [PATCH 7/9] hw/cxl: Add release-time teardown for direct-mapped extents Alireza Sanaee via qemu development
2026-03-25 18:42 ` [PATCH 8/9] hw/cxl: Add tag-based dynamic-capacity release support Alireza Sanaee via qemu development
2026-03-25 18:42 ` [PATCH 9/9] hw/cxl: Add QMP status query for dynamic-capacity extent release Alireza Sanaee via qemu development
2026-03-26 15:15 ` Markus Armbruster
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