From: Alireza Sanaee via qemu development <qemu-devel@nongnu.org>
To: <qemu-devel@nongnu.org>
Cc: <anisa.su@samsung.com>, <armbru@redhat.com>,
<berrange@redhat.com>, <eblake@redhat.com>,
<jonathan.cameron@huawei.com>, <linux-cxl@vger.kernel.org>,
<linuxarm@huawei.com>, <lizhijian@fujitsu.com>, <mst@redhat.com>,
<pbonzini@redhat.com>, <gourry@gourry.net>, <nifan.cxl@gmail.com>,
<me@linux.beauty>
Subject: [PATCH 5/9] hw/cxl: Map lazy memory backend after host acceptance
Date: Wed, 25 Mar 2026 18:42:53 +0000 [thread overview]
Message-ID: <20260325184259.366-6-alireza.sanaee@huawei.com> (raw)
In-Reply-To: <20260325184259.366-1-alireza.sanaee@huawei.com>
In the dc-regions-total-size flow, a requested extent is not backed when it
is queued. It becomes usable only after the host accepts it with Add
Dynamic Capacity Response.
Use that response path to look up the first pending group's metadata for
each accepted extent, enable the selected host backend, and move the
backend and fixed-window references onto the committed extent list. The
accepted range is then marked backed just like the non-lazy path.
This wires host acceptance to the lazy backend lifecycle and leaves the
fixed-window direct aliasing to the following patch.
Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
---
hw/cxl/cxl-mailbox-utils.c | 76 ++++++++++++++++++++++++++++++++++++--
1 file changed, 73 insertions(+), 3 deletions(-)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index c5427adb3a..cc7be6e68c 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -3668,6 +3668,28 @@ static CXLRetCode cxl_detect_malformed_extent_list(CXLType3Dev *ct3d,
return CXL_MBOX_SUCCESS;
}
+/* Find extent details (backend, window, tag, rid) in the first pending group */
+static bool cxl_extent_find_extent_detail(CXLDCExtentGroupList *list,
+ uint64_t start_dpa, uint64_t len,
+ uint8_t *tag, HostMemoryBackend **hmb,
+ struct CXLFixedWindow **fw, int *rid)
+{
+ CXLDCExtent *ent;
+ CXLDCExtentGroup *group = QTAILQ_FIRST(list);
+
+ QTAILQ_FOREACH(ent, &group->list, node) {
+ if (ent->start_dpa == start_dpa && ent->len == len) {
+ *fw = ent->fw;
+ *hmb = ent->hm;
+ memcpy(tag, ent->tag, 0x10);
+ *rid = ent->rid;
+ return true;
+ }
+ }
+
+ return false;
+}
+
static CXLRetCode cxl_dcd_add_dyn_cap_rsp_dry_run(CXLType3Dev *ct3d,
const CXLUpdateDCExtentListInPl *in)
{
@@ -3718,8 +3740,12 @@ static CXLRetCode cmd_dcd_add_dyn_cap_rsp(const struct cxl_cmd *cmd,
CXLUpdateDCExtentListInPl *in = (void *)payload_in;
CXLType3Dev *ct3d = CXL_TYPE3(cci->d);
CXLDCExtentList *extent_list = &ct3d->dc.extents;
+ struct CXLFixedWindow *fw;
+ HostMemoryBackend *hmb_dc;
+ uint8_t tag[0x10];
uint32_t i, num;
uint64_t dpa, len;
+ int rid;
CXLRetCode ret;
if (len_in < sizeof(*in)) {
@@ -3756,10 +3782,54 @@ static CXLRetCode cmd_dcd_add_dyn_cap_rsp(const struct cxl_cmd *cmd,
for (i = 0; i < in->num_entries_updated; i++) {
dpa = in->updated_entries[i].start_dpa;
len = in->updated_entries[i].len;
+ if (ct3d->dc.total_capacity_cmd) {
+ bool found;
+ MemoryRegion *mr;
+
+ found = cxl_extent_find_extent_detail(&ct3d->dc.extents_pending,
+ dpa, len, tag,
+ &hmb_dc, &fw, &rid);
+
+ /*
+ * Host accepted an extent where device lacks details including
+ * wrong DPA or wrong length.
+ */
+ if (!found) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Could not find the extent detail for DPA 0x%"
+ PRIx64 " LEN 0x%" PRIx64 "\n", dpa, len);
+ return CXL_MBOX_INVALID_PA;
+ }
+
+ /* The host memory backend should not be already mapped */
+ if (host_memory_backend_is_mapped(hmb_dc)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "The host memory backend for DPA 0x%" PRIx64
+ " LEN 0x%" PRIx64 " is already mapped\n",
+ dpa, len);
+ return CXL_MBOX_INVALID_PA;
+ }
- cxl_insert_extent_to_extent_list(extent_list,
- NULL, NULL, dpa, len,
- NULL, 0, 0);
+ mr = host_memory_backend_get_memory(hmb_dc);
+ if (!mr) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Could not get memory region from "
+ "host memory backend\n");
+ return CXL_MBOX_INVALID_PA;
+ }
+
+ memory_region_set_nonvolatile(mr, false);
+ memory_region_set_enabled(mr, true);
+ host_memory_backend_set_mapped(hmb_dc, true);
+
+ cxl_insert_extent_to_extent_list(extent_list,
+ hmb_dc, fw, dpa, len,
+ NULL, 0, rid);
+ } else {
+ cxl_insert_extent_to_extent_list(extent_list,
+ NULL, NULL, dpa, len,
+ NULL, 0, -1);
+ }
ct3d->dc.total_extent_count += 1;
ct3d->dc.nr_extents_accepted += 1;
ct3_set_region_block_backed(ct3d, dpa, len);
--
2.50.1 (Apple Git-155)
next prev parent reply other threads:[~2026-03-25 18:46 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-25 18:42 [QEMU PATCH 0/9] Application Specific Tagged Memory Support in CXL Type 3 Devices Alireza Sanaee via qemu development
2026-03-25 18:42 ` [PATCH 1/9] hw/mem: Add tag support to generic host memory backends Alireza Sanaee via qemu development
2026-03-26 10:42 ` Markus Armbruster
2026-03-26 11:29 ` Alireza Sanaee via qemu development
2026-03-26 13:01 ` Markus Armbruster
2026-03-26 13:04 ` Alireza Sanaee via qemu development
2026-03-25 18:42 ` [PATCH 2/9] hw/cxl: Allow initializing type3 device with no backing device Alireza Sanaee via qemu development
2026-03-25 18:42 ` [PATCH 3/9] hw/cxl: Hook up tagged host memory backends at runtime for DC extents Alireza Sanaee via qemu development
2026-03-25 18:42 ` [PATCH 4/9] hw/cxl: Carry backend metadata in DC extent records Alireza Sanaee via qemu development
2026-03-25 18:42 ` Alireza Sanaee via qemu development [this message]
2026-03-25 18:42 ` [PATCH 6/9] hw/cxl: Create direct fixed-window aliases for accepted extents Alireza Sanaee via qemu development
2026-03-25 18:42 ` [PATCH 7/9] hw/cxl: Add release-time teardown for direct-mapped extents Alireza Sanaee via qemu development
2026-03-25 18:42 ` [PATCH 8/9] hw/cxl: Add tag-based dynamic-capacity release support Alireza Sanaee via qemu development
2026-03-25 18:42 ` [PATCH 9/9] hw/cxl: Add QMP status query for dynamic-capacity extent release Alireza Sanaee via qemu development
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