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Wed, 22 Apr 2026 20:43:44 +0000 Received: from CY3PR12MB9555.namprd12.prod.outlook.com ([fe80::fdb2:266d:ee2b:8d1e]) by CY3PR12MB9555.namprd12.prod.outlook.com ([fe80::fdb2:266d:ee2b:8d1e%6]) with mapi id 15.20.9846.016; Wed, 22 Apr 2026 20:43:44 +0000 From: Nathan Chen To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Eric Auger , Peter Maydell , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Zhao Liu , Shameer Kolothum , Matt Ochs , Nicolin Chen , Nathan Chen Subject: [PATCH v2 0/7] hw/arm/smmuv3-accel: Resolve AUTO properties Date: Wed, 22 Apr 2026 13:43:28 -0700 Message-ID: <20260422204335.23116-1-nathanc@nvidia.com> X-Mailer: git-send-email 2.43.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SJ0PR03CA0212.namprd03.prod.outlook.com (2603:10b6:a03:39f::7) To CY3PR12MB9555.namprd12.prod.outlook.com (2603:10b6:930:10a::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY3PR12MB9555:EE_|SA1PR12MB7368:EE_ X-MS-Office365-Filtering-Correlation-Id: d0eab06e-d49b-4e7e-eca0-08dea0afd88f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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envelope-from=nathanc@nvidia.com; helo=PH7PR06CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, This series introduces support for resolving 'auto' for arm-smmuv3 accelerated mode's ATS, RIL, SSIDSIZE, and OAS feature properties based on host IOMMU capabilities. This is dependent on the series [0] for changing these property types to accept 'auto' values. Accelerated SMMUv3 Address Translation Services support is derived from IDR0, Range Invalidation support is derived from IDR3, Substream ID size is derived from IDR1, and output address space is derived from IDR5. The default values are set to 'auto' for all properties. If accel=off and the values are set to 'auto' or are omitted and resolve to 'auto', the default property values defined in smmuv3_init_id_regs() for OAS and RIL will remain unchanged, while SSIDSIZE and ATS values will remain initialized at 0. A complete branch can be found here: https://github.com/NathanChenNVIDIA/qemu/tree/smmuv3-accel-auto-resolve-v2 Please take a look and let me know your feedback. Thanks, Nathan [0] https://lore.kernel.org/qemu-arm/20260323182454.1416110-1-nathanc@nvidia.com/ Example usage: qemu-system-aarch64 \ -object iommufd,id=iommufd0 \ -machine virt,accel=kvm,gic-version=3,ras=on,highmem-mmio-size=4T \ -cpu host -smp cpus=4 -m size=16G -nographic \ -object memory-backend-ram,size=16G,id=m0 \ -numa node,memdev=m0,cpus=0-3,nodeid=0 \ -numa node,nodeid=1 -numa node,nodeid=2 -numa node,nodeid=3 -numa node,nodeid=4 \ -numa node,nodeid=5 -numa node,nodeid=6 -numa node,nodeid=7 -numa node,nodeid=8 \ -device pxb-pcie,id=pcie.1,bus_nr=1,bus=pcie.0,numa_node=0 \ -device arm-smmuv3,primary-bus=pcie.1,id=smmuv3.1,accel=on,ats=auto,ssidsize=auto,ril=auto,oas=auto \ -device pcie-root-port,id=pcie.port1,bus=pcie.1,chassis=1,io-reserve=0 \ -device vfio-pci-nohotplug,host=0009:06:00.0,bus=pcie.port1,rombar=0,id=dev0,iommufd=iommufd0,ats=auto \ -object acpi-generic-initiator,id=gi0,pci-dev=dev0,node=1 \ -object acpi-generic-initiator,id=gi1,pci-dev=dev0,node=2 \ -object acpi-generic-initiator,id=gi2,pci-dev=dev0,node=3 \ -object acpi-generic-initiator,id=gi3,pci-dev=dev0,node=4 \ -object acpi-generic-initiator,id=gi4,pci-dev=dev0,node=5 \ -object acpi-generic-initiator,id=gi5,pci-dev=dev0,node=6 \ -object acpi-generic-initiator,id=gi6,pci-dev=dev0,node=7 \ -object acpi-generic-initiator,id=gi7,pci-dev=dev0,node=8 \ -bios /usr/share/AAVMF/AAVMF_CODE.fd \ -device nvme,drive=nvme0,serial=deadbeaf1,bus=pcie.0 \ -drive file=/var/lib/libvirt/images/guest.qcow2,index=0,media=disk,format=qcow2,if=none,id=nvme0 \ -device e1000,romfile=/usr/local/share/qemu/efi-e1000.rom,netdev=net0,bus=pcie.0 \ -netdev user,id=net0,hostfwd=tcp::5558-:22,hostfwd=tcp::5586-:5586 Testing: Basic sanity testing was performed on an NVIDIA Grace platform with GPU device assignment and running CUDA test apps on the guest. Observed the feature properties being set based on host IOMMU capabilities. Verified that the VM boot will fail without a cold-plugged device, and that a hot-plugged device re-uses the resolved values from the initial cold-plug. Additional testing and feedback are welcome. Nathan Chen (7): hw/arm/smmuv3-accel: Add helper for resolving auto parameters hw/arm/smmuv3-accel: Implement "auto" value for "ats" hw/arm/smmuv3-accel: Implement "auto" value for "ril" hw/arm/smmuv3-accel: Implement "auto" value for "ssidsize" hw/arm/smmuv3-accel: Implement "auto" value for "oas" hw/arm/smmuv3: Set default ats, ril, ssidsize, oas to auto qemu-options.hx: Support "auto" for accel SMMUv3 properties hw/arm/smmuv3-accel.c | 80 ++++++++++++++++++++++++++++++++++++++++- hw/arm/smmuv3-accel.h | 2 ++ hw/arm/smmuv3.c | 63 +++++++++++++++----------------- hw/core/machine.c | 8 +++++ include/hw/arm/smmuv3.h | 2 ++ qemu-options.hx | 33 +++++++++++------ 6 files changed, 143 insertions(+), 45 deletions(-) -- 2.43.0