From: Stefan Hajnoczi <stefanha@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org
Subject: Re: [PULL 00/67] target-arm queue
Date: Mon, 11 May 2026 10:21:33 -0400 [thread overview]
Message-ID: <20260511142133.GA520528@fedora> (raw)
In-Reply-To: <20260507155154.1886557-1-peter.maydell@linaro.org>
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Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/11.1 for any user-visible changes.
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prev parent reply other threads:[~2026-05-11 14:22 UTC|newest]
Thread overview: 69+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-07 15:50 [PULL 00/67] target-arm queue Peter Maydell
2026-05-07 15:50 ` [PULL 01/67] qom/object: Add object_resolve_and_typecheck() Peter Maydell
2026-05-07 15:50 ` [PULL 02/67] hw/core: Permit devices to define an array of link properties Peter Maydell
2026-05-07 15:50 ` [PULL 03/67] hw/intc: Skeleton of GICv5 IRS classes Peter Maydell
2026-05-07 15:50 ` [PULL 04/67] hw/arm/Kconfig: select ARM_GICV5 for ARM_VIRT board Peter Maydell
2026-05-07 15:50 ` [PULL 05/67] hw/intc/arm_gicv5: Implement skeleton code for IRS register frames Peter Maydell
2026-05-07 15:50 ` [PULL 06/67] hw/intc/arm_gicv5: Add migration blocker Peter Maydell
2026-05-07 15:50 ` [PULL 07/67] hw/intc/arm_gicv5: Create and validate QOM properties Peter Maydell
2026-05-07 15:50 ` [PULL 08/67] hw/intc/arm_gicv5: Create inbound GPIO lines for SPIs Peter Maydell
2026-05-07 15:50 ` [PULL 09/67] hw/intc/arm_gicv5: Define macros for config frame registers Peter Maydell
2026-05-07 15:50 ` [PULL 10/67] hw/intc/arm_gicv5: Implement IRS ID regs Peter Maydell
2026-05-07 15:50 ` [PULL 11/67] hw/intc/arm_gicv5: Add link property for MemoryRegion for DMA Peter Maydell
2026-05-07 15:50 ` [PULL 12/67] hw/intc/arm_gicv5: Implement gicv5_class_name() Peter Maydell
2026-05-07 15:51 ` [PULL 13/67] hw/intc/arm_gicv5: Add defines for GICv5 architected PPIs Peter Maydell
2026-05-07 15:51 ` [PULL 14/67] target/arm: GICv5 cpuif: Initial skeleton and GSB barrier insns Peter Maydell
2026-05-07 15:51 ` [PULL 15/67] target/arm: Set up pointer to GICv5 in each CPU Peter Maydell
2026-05-07 15:51 ` [PULL 16/67] hw/intc/arm_gicv5: Implement IRS_IST_{BASER, STATUSR, CFGR} Peter Maydell
2026-05-07 15:51 ` [PULL 17/67] hw/intc/arm_gicv5: Cache LPI IST config in a struct Peter Maydell
2026-05-07 15:51 ` [PULL 18/67] hw/intc/arm_gicv5: Implement gicv5_set_priority() Peter Maydell
2026-05-07 15:51 ` [PULL 19/67] target/arm: GICv5 cpuif: Implement the GIC CDPRI instruction Peter Maydell
2026-05-07 15:51 ` [PULL 20/67] hw/intc/arm_gicv5: Implement IRS_MAP_L2_ISTR Peter Maydell
2026-05-07 15:51 ` [PULL 21/67] hw/intc/arm_gicv5: Implement remaining set-config functions Peter Maydell
2026-05-07 15:51 ` [PULL 22/67] target/arm: GICv5 cpuif: Implement GIC CD* insns for setting config Peter Maydell
2026-05-07 15:51 ` [PULL 23/67] hw/intc/arm_gicv5: Create backing state for SPIs Peter Maydell
2026-05-07 15:51 ` [PULL 24/67] hw/intc/arm_gicv5: Make gicv5_set_* update SPI state Peter Maydell
2026-05-07 15:51 ` [PULL 25/67] hw/intc/arm_gicv5: Implement gicv5_request_config() Peter Maydell
2026-05-07 15:51 ` [PULL 26/67] target/arm: GICv5 cpuif: Implement GIC CDRCFG and ICC_ICSR_EL1 Peter Maydell
2026-05-07 15:51 ` [PULL 27/67] hw/intc/arm_gicv5: Implement IRS_SPI_{SELR, STATUSR, CFGR, DOMAINR} Peter Maydell
2026-05-07 15:51 ` [PULL 28/67] hw/intc/arm_gicv5: Update SPI state for CLEAR/SET events Peter Maydell
2026-05-07 15:51 ` [PULL 29/67] hw/intc/arm_gicv5: Implement IRS_CR0 and IRS_CR1 Peter Maydell
2026-05-07 15:51 ` [PULL 30/67] hw/intc/arm_gicv5: Implement IRS_SYNCR and IRS_SYNC_STATUSR Peter Maydell
2026-05-07 15:51 ` [PULL 31/67] hw/intc/arm_gicv5: Implement IRS_PE_{CR0, SELR, STATUSR} Peter Maydell
2026-05-07 15:51 ` [PULL 32/67] hw/intc/arm_gicv5: Implement CoreSight ID registers Peter Maydell
2026-05-07 15:51 ` [PULL 33/67] hw/intc/arm_gicv5: Cache pending LPIs in a hash table Peter Maydell
2026-05-07 15:51 ` [PULL 34/67] target/arm: GICv5 cpuif: Implement ICC_IAFFIDR_EL1 Peter Maydell
2026-05-07 15:51 ` [PULL 35/67] target/arm: GICv5 cpuif: Implement ICC_IDR0_EL1 Peter Maydell
2026-05-07 15:51 ` [PULL 36/67] target/arm: GICv5 cpuif: Implement GICv5 PPI active set/clear registers Peter Maydell
2026-05-07 15:51 ` [PULL 37/67] target/arm: GICv5 cpuif: Implement PPI handling mode register Peter Maydell
2026-05-07 15:51 ` [PULL 38/67] target/arm: GICv5 cpuif: Implement PPI pending status registers Peter Maydell
2026-05-07 15:51 ` [PULL 39/67] target/arm: GICv5 cpuif: Implement PPI enable register Peter Maydell
2026-05-07 15:51 ` [PULL 40/67] target/arm: GICv5 cpuif: Implement PPI priority registers Peter Maydell
2026-05-07 15:51 ` [PULL 41/67] target/arm: GICv5 cpuif: Implement ICC_APR_EL1 and ICC_HAPR_EL1 Peter Maydell
2026-05-07 15:51 ` [PULL 42/67] target/arm: GICv5 cpuif: Calculate the highest priority PPI Peter Maydell
2026-05-07 15:51 ` [PULL 43/67] hw/intc/arm_gicv5: Calculate HPPI in the IRS Peter Maydell
2026-05-07 15:51 ` [PULL 44/67] target/arm: GICv5 cpuif: Implement ICC_CR0_EL1 Peter Maydell
2026-05-07 15:51 ` [PULL 45/67] target/arm: GICv5 cpuif: Implement ICC_PCR_EL1 Peter Maydell
2026-05-07 15:51 ` [PULL 46/67] target/arm: GICv5 cpuif: Implement ICC_HPPIR_EL1 Peter Maydell
2026-05-07 15:51 ` [PULL 47/67] hw/intc/arm_gicv5: Implement Activate command Peter Maydell
2026-05-07 15:51 ` [PULL 48/67] target/arm: GICv5 cpuif: Implement GICR CDIA command Peter Maydell
2026-05-07 15:51 ` [PULL 49/67] target/arm: GICv5 cpuif: Implement GIC CDEOI Peter Maydell
2026-05-07 15:51 ` [PULL 50/67] hw/intc/arm_gicv5: Implement Deactivate command Peter Maydell
2026-05-07 15:51 ` [PULL 51/67] target/arm: GICv5 cpuif: Implement GIC CDDI Peter Maydell
2026-05-07 15:51 ` [PULL 52/67] target/arm: GICv5 cpuif: Signal IRQ or FIQ Peter Maydell
2026-05-07 15:51 ` [PULL 53/67] target/arm: Connect internal interrupt sources up as GICv5 PPIs Peter Maydell
2026-05-07 15:51 ` [PULL 54/67] target/arm: Add has_gcie property to enable FEAT_GCIE Peter Maydell
2026-05-07 15:51 ` [PULL 55/67] hw/intc/arm_gicv3_cpuif: Don't allow GICv3 if CPU has GICv5 cpuif Peter Maydell
2026-05-07 15:51 ` [PULL 56/67] hw/arm/virt: Remember CPU phandles rather than looking them up by name Peter Maydell
2026-05-07 15:51 ` [PULL 57/67] hw/arm/virt: Move MSI controller creation out of create_gic() Peter Maydell
2026-05-07 15:51 ` [PULL 58/67] hw/arm/virt: Pull "wire CPU interrupts" " Peter Maydell
2026-05-07 15:51 ` [PULL 59/67] hw/arm/virt: Split GICv2 and GICv3/4 creation Peter Maydell
2026-05-07 15:51 ` [PULL 60/67] hw/arm/virt: Create and connect GICv5 Peter Maydell
2026-05-07 15:51 ` [PULL 61/67] hw/arm/virt: Advertise GICv5 in the DTB Peter Maydell
2026-05-07 15:51 ` [PULL 62/67] hw/arm/virt: Handle GICv5 in interrupt bindings for PPIs Peter Maydell
2026-05-07 15:51 ` [PULL 63/67] hw/arm/virt: Use correct interrupt type for GICv5 SPIs in the DTB Peter Maydell
2026-05-07 15:51 ` [PULL 64/67] hw/arm/virt: Enable GICv5 CPU interface when using GICv5 Peter Maydell
2026-05-07 15:51 ` [PULL 65/67] hw/arm/virt: Allow user to select GICv5 Peter Maydell
2026-05-07 15:51 ` [PULL 66/67] target/arm: Report IL=0 for Thumb 16-bit BKPT insn Peter Maydell
2026-05-07 15:51 ` [PULL 67/67] hw/misc/bcm2835_rng: Specify valid memory access sizes Peter Maydell
2026-05-11 14:21 ` Stefan Hajnoczi [this message]
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