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[94.175.9.129]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49d26d4e3f3sm328384495e9.15.2026.09.13.00.03.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Sep 2026 00:03:26 -0700 (PDT) From: Stafford Horne To: QEMU Development Cc: Linux OpenRISC , Richard Henderson , Stefan Hajnoczi , =?UTF-8?q?Ali=20Ahmet=20Memi=C5=9F?= , Stafford Horne Subject: [PULL 1/1] target/or1k: Implement l.extws and l.extwz Date: Sun, 13 Sep 2026 08:03:03 +0100 Message-ID: <20260913070303.1010504-2-shorne@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260913070303.1010504-1-shorne@gmail.com> References: <20260913070303.1010504-1-shorne@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:31::10; envelope-from=shorne@gmail.com; helo=mail-wm2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Ali Ahmet Memiş l.extws and l.extwz belong to the ORBIS32 instruction set, but the decoder has no entries for them, so they raise an illegal instruction exception on every CPU model. On a 32-bit implementation both are register moves: there is nothing above bit 31 to extend into. Implement them as such. Found while writing an OpenRISC port of Valgrind. Signed-off-by: Ali Ahmet Memiş Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- target/or1k/disas.c | 2 ++ target/or1k/insns.decode | 2 ++ target/or1k/translate.c | 14 ++++++++++++++ 3 files changed, 18 insertions(+) diff --git a/target/or1k/disas.c b/target/or1k/disas.c index dc025bd64d..0a46d68d30 100644 --- a/target/or1k/disas.c +++ b/target/or1k/disas.c @@ -71,6 +71,8 @@ INSN(exths, "r%d, r%d", a->d, a->a) INSN(extbs, "r%d, r%d", a->d, a->a) INSN(exthz, "r%d, r%d", a->d, a->a) INSN(extbz, "r%d, r%d", a->d, a->a) +INSN(extws, "r%d, r%d", a->d, a->a) +INSN(extwz, "r%d, r%d", a->d, a->a) INSN(cmov, "r%d, r%d, r%d", a->d, a->a, a->b) INSN(ff1, "r%d, r%d", a->d, a->a) INSN(fl1, "r%d, r%d", a->d, a->a) diff --git a/target/or1k/insns.decode b/target/or1k/insns.decode index 0d6f7c29f8..cbf8af7f8b 100644 --- a/target/or1k/insns.decode +++ b/target/or1k/insns.decode @@ -112,6 +112,8 @@ l_exths 111000 d:5 a:5 ----- - 0000 -- 1100 l_extbs 111000 d:5 a:5 ----- - 0001 -- 1100 l_exthz 111000 d:5 a:5 ----- - 0010 -- 1100 l_extbz 111000 d:5 a:5 ----- - 0011 -- 1100 +l_extws 111000 d:5 a:5 ----- - 0000 -- 1101 +l_extwz 111000 d:5 a:5 ----- - 0001 -- 1101 l_add 111000 d:5 a:5 b:5 - 00 ---- 0000 l_addc 111000 d:5 a:5 b:5 - 00 ---- 0001 diff --git a/target/or1k/translate.c b/target/or1k/translate.c index eb4485312f..e00ef45b9b 100644 --- a/target/or1k/translate.c +++ b/target/or1k/translate.c @@ -502,6 +502,20 @@ static bool trans_l_extbz(DisasContext *dc, arg_da *a) return true; } +static bool trans_l_extws(DisasContext *dc, arg_da *a) +{ + check_r0_write(dc, a->d); + tcg_gen_mov_i32(cpu_R(dc, a->d), cpu_R(dc, a->a)); + return true; +} + +static bool trans_l_extwz(DisasContext *dc, arg_da *a) +{ + check_r0_write(dc, a->d); + tcg_gen_mov_i32(cpu_R(dc, a->d), cpu_R(dc, a->a)); + return true; +} + static bool trans_l_cmov(DisasContext *dc, arg_dab *a) { check_r0_write(dc, a->d); -- 2.53.0