* [PATCH v2] target/riscv: Add isa extenstion strings to the device tree
@ 2022-02-16 0:09 Atish Patra
2022-02-16 3:18 ` Anup Patel
2022-02-16 11:42 ` Heiko Stübner
0 siblings, 2 replies; 4+ messages in thread
From: Atish Patra @ 2022-02-16 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, Heiko Stubner, Bin Meng, Atish Patra,
Alistair Francis, Palmer Dabbelt
The Linux kernel parses the ISA extensions from "riscv,isa" DT
property. It used to parse only the single letter base extensions
until now. A generic ISA extension parsing framework was proposed[1]
recently that can parse multi-letter ISA extensions as well.
Generate the extended ISA string by appending the available ISA extensions
to the "riscv,isa" string if it is enabled so that kernel can process it.
[1] https://lkml.org/lkml/2022/2/15/263
Suggested-by: Heiko Stubner <heiko@sntech.de>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
Changes from v1->v2:
1. Improved the code redability by using arrays instead of individual check
---
target/riscv/cpu.c | 35 ++++++++++++++++++++++++++++++++++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b0a40b83e7a8..9bf8923f164b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -34,6 +34,13 @@
/* RISC-V CPU definitions */
+/* This includes the null terminated character '\0' */
+#define MAX_ISA_EXT_LEN 256
+struct isa_ext_data {
+ const char *name;
+ bool enabled;
+};
+
static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
const char * const riscv_int_regnames[] = {
@@ -881,10 +888,35 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
device_class_set_props(dc, riscv_cpu_properties);
}
+static void riscv_isa_string_ext(RISCVCPU *cpu, char *isa_str, int max_str_len)
+{
+ int offset = strnlen(isa_str, max_str_len);
+ int i;
+ struct isa_ext_data isa_edata_arr[] = {
+ { "svpbmt", cpu->cfg.ext_svpbmt },
+ { "svinval", cpu->cfg.ext_svinval },
+ { "svnapot", cpu->cfg.ext_svnapot },
+ };
+
+ for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
+ if (!isa_edata_arr[i].enabled) {
+ continue;
+ }
+ /* check available space */
+ if ((offset + strlen(isa_edata_arr[i].name) + 1) > max_str_len) {
+ qemu_log("No space left to append isa extension");
+ return;
+ }
+ offset += snprintf(isa_str + offset, max_str_len, "_%s",
+ isa_edata_arr[i].name);
+ }
+}
+
char *riscv_isa_string(RISCVCPU *cpu)
{
int i;
- const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
+ const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) +
+ MAX_ISA_EXT_LEN;
char *isa_str = g_new(char, maxlen);
char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
for (i = 0; i < sizeof(riscv_exts); i++) {
@@ -893,6 +925,7 @@ char *riscv_isa_string(RISCVCPU *cpu)
}
}
*p = '\0';
+ riscv_isa_string_ext(cpu, isa_str, maxlen);
return isa_str;
}
--
2.30.2
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH v2] target/riscv: Add isa extenstion strings to the device tree
2022-02-16 0:09 [PATCH v2] target/riscv: Add isa extenstion strings to the device tree Atish Patra
@ 2022-02-16 3:18 ` Anup Patel
2022-02-22 22:28 ` Atish Patra
2022-02-16 11:42 ` Heiko Stübner
1 sibling, 1 reply; 4+ messages in thread
From: Anup Patel @ 2022-02-16 3:18 UTC (permalink / raw)
To: Atish Patra
Cc: open list:RISC-V, Heiko Stubner, Bin Meng, QEMU Developers,
Alistair Francis, Palmer Dabbelt
On Wed, Feb 16, 2022 at 5:39 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> The Linux kernel parses the ISA extensions from "riscv,isa" DT
> property. It used to parse only the single letter base extensions
> until now. A generic ISA extension parsing framework was proposed[1]
> recently that can parse multi-letter ISA extensions as well.
>
> Generate the extended ISA string by appending the available ISA extensions
> to the "riscv,isa" string if it is enabled so that kernel can process it.
>
> [1] https://lkml.org/lkml/2022/2/15/263
>
> Suggested-by: Heiko Stubner <heiko@sntech.de>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
> Changes from v1->v2:
> 1. Improved the code redability by using arrays instead of individual check
> ---
> target/riscv/cpu.c | 35 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 34 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b0a40b83e7a8..9bf8923f164b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -34,6 +34,13 @@
>
> /* RISC-V CPU definitions */
>
> +/* This includes the null terminated character '\0' */
> +#define MAX_ISA_EXT_LEN 256
> +struct isa_ext_data {
> + const char *name;
> + bool enabled;
> +};
> +
> static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
>
> const char * const riscv_int_regnames[] = {
> @@ -881,10 +888,35 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> device_class_set_props(dc, riscv_cpu_properties);
> }
>
> +static void riscv_isa_string_ext(RISCVCPU *cpu, char *isa_str, int max_str_len)
> +{
> + int offset = strnlen(isa_str, max_str_len);
> + int i;
> + struct isa_ext_data isa_edata_arr[] = {
> + { "svpbmt", cpu->cfg.ext_svpbmt },
> + { "svinval", cpu->cfg.ext_svinval },
> + { "svnapot", cpu->cfg.ext_svnapot },
> + };
> +
> + for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
> + if (!isa_edata_arr[i].enabled) {
> + continue;
> + }
> + /* check available space */
> + if ((offset + strlen(isa_edata_arr[i].name) + 1) > max_str_len) {
> + qemu_log("No space left to append isa extension");
> + return;
> + }
> + offset += snprintf(isa_str + offset, max_str_len, "_%s",
> + isa_edata_arr[i].name);
You don't need to use snprintf() and MAX_ISA_EXT_LEN if you
use g_strconcat() for creating new concat strings and freeing
original string using g_free().
Regards,
Anup
> + }
> +}
> +
> char *riscv_isa_string(RISCVCPU *cpu)
> {
> int i;
> - const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
> + const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) +
> + MAX_ISA_EXT_LEN;
> char *isa_str = g_new(char, maxlen);
> char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
> for (i = 0; i < sizeof(riscv_exts); i++) {
> @@ -893,6 +925,7 @@ char *riscv_isa_string(RISCVCPU *cpu)
> }
> }
> *p = '\0';
> + riscv_isa_string_ext(cpu, isa_str, maxlen);
> return isa_str;
> }
>
> --
> 2.30.2
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v2] target/riscv: Add isa extenstion strings to the device tree
2022-02-16 3:18 ` Anup Patel
@ 2022-02-22 22:28 ` Atish Patra
0 siblings, 0 replies; 4+ messages in thread
From: Atish Patra @ 2022-02-22 22:28 UTC (permalink / raw)
To: Anup Patel
Cc: open list:RISC-V, Heiko Stubner, Bin Meng, QEMU Developers,
Alistair Francis, Palmer Dabbelt
On Tue, Feb 15, 2022 at 7:19 PM Anup Patel <anup@brainfault.org> wrote:
>
> On Wed, Feb 16, 2022 at 5:39 AM Atish Patra <atishp@rivosinc.com> wrote:
> >
> > The Linux kernel parses the ISA extensions from "riscv,isa" DT
> > property. It used to parse only the single letter base extensions
> > until now. A generic ISA extension parsing framework was proposed[1]
> > recently that can parse multi-letter ISA extensions as well.
> >
> > Generate the extended ISA string by appending the available ISA extensions
> > to the "riscv,isa" string if it is enabled so that kernel can process it.
> >
> > [1] https://lkml.org/lkml/2022/2/15/263
> >
> > Suggested-by: Heiko Stubner <heiko@sntech.de>
> > Signed-off-by: Atish Patra <atishp@rivosinc.com>
> > ---
> > Changes from v1->v2:
> > 1. Improved the code redability by using arrays instead of individual check
> > ---
> > target/riscv/cpu.c | 35 ++++++++++++++++++++++++++++++++++-
> > 1 file changed, 34 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index b0a40b83e7a8..9bf8923f164b 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -34,6 +34,13 @@
> >
> > /* RISC-V CPU definitions */
> >
> > +/* This includes the null terminated character '\0' */
> > +#define MAX_ISA_EXT_LEN 256
> > +struct isa_ext_data {
> > + const char *name;
> > + bool enabled;
> > +};
> > +
> > static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
> >
> > const char * const riscv_int_regnames[] = {
> > @@ -881,10 +888,35 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> > device_class_set_props(dc, riscv_cpu_properties);
> > }
> >
> > +static void riscv_isa_string_ext(RISCVCPU *cpu, char *isa_str, int max_str_len)
> > +{
> > + int offset = strnlen(isa_str, max_str_len);
> > + int i;
> > + struct isa_ext_data isa_edata_arr[] = {
> > + { "svpbmt", cpu->cfg.ext_svpbmt },
> > + { "svinval", cpu->cfg.ext_svinval },
> > + { "svnapot", cpu->cfg.ext_svnapot },
> > + };
> > +
> > + for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
> > + if (!isa_edata_arr[i].enabled) {
> > + continue;
> > + }
> > + /* check available space */
> > + if ((offset + strlen(isa_edata_arr[i].name) + 1) > max_str_len) {
> > + qemu_log("No space left to append isa extension");
> > + return;
> > + }
> > + offset += snprintf(isa_str + offset, max_str_len, "_%s",
> > + isa_edata_arr[i].name);
>
> You don't need to use snprintf() and MAX_ISA_EXT_LEN if you
> use g_strconcat() for creating new concat strings and freeing
> original string using g_free().
>
Yeah. That is better. I have reimplemented this part in v3.
> Regards,
> Anup
>
> > + }
> > +}
> > +
> > char *riscv_isa_string(RISCVCPU *cpu)
> > {
> > int i;
> > - const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
> > + const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) +
> > + MAX_ISA_EXT_LEN;
> > char *isa_str = g_new(char, maxlen);
> > char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
> > for (i = 0; i < sizeof(riscv_exts); i++) {
> > @@ -893,6 +925,7 @@ char *riscv_isa_string(RISCVCPU *cpu)
> > }
> > }
> > *p = '\0';
> > + riscv_isa_string_ext(cpu, isa_str, maxlen);
> > return isa_str;
> > }
> >
> > --
> > 2.30.2
> >
> >
>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v2] target/riscv: Add isa extenstion strings to the device tree
2022-02-16 0:09 [PATCH v2] target/riscv: Add isa extenstion strings to the device tree Atish Patra
2022-02-16 3:18 ` Anup Patel
@ 2022-02-16 11:42 ` Heiko Stübner
1 sibling, 0 replies; 4+ messages in thread
From: Heiko Stübner @ 2022-02-16 11:42 UTC (permalink / raw)
To: qemu-devel, Atish Patra
Cc: Atish Patra, Alistair Francis, Bin Meng, Palmer Dabbelt,
qemu-riscv
Am Mittwoch, 16. Februar 2022, 01:09:04 CET schrieb Atish Patra:
> The Linux kernel parses the ISA extensions from "riscv,isa" DT
> property. It used to parse only the single letter base extensions
> until now. A generic ISA extension parsing framework was proposed[1]
> recently that can parse multi-letter ISA extensions as well.
>
> Generate the extended ISA string by appending the available ISA extensions
> to the "riscv,isa" string if it is enabled so that kernel can process it.
>
> [1] https://lkml.org/lkml/2022/2/15/263
>
> Suggested-by: Heiko Stubner <heiko@sntech.de>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
> ---
> Changes from v1->v2:
> 1. Improved the code redability by using arrays instead of individual check
> ---
> target/riscv/cpu.c | 35 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 34 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b0a40b83e7a8..9bf8923f164b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -34,6 +34,13 @@
>
> /* RISC-V CPU definitions */
>
> +/* This includes the null terminated character '\0' */
> +#define MAX_ISA_EXT_LEN 256
> +struct isa_ext_data {
> + const char *name;
> + bool enabled;
> +};
> +
> static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
>
> const char * const riscv_int_regnames[] = {
> @@ -881,10 +888,35 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> device_class_set_props(dc, riscv_cpu_properties);
> }
>
> +static void riscv_isa_string_ext(RISCVCPU *cpu, char *isa_str, int max_str_len)
> +{
> + int offset = strnlen(isa_str, max_str_len);
> + int i;
> + struct isa_ext_data isa_edata_arr[] = {
> + { "svpbmt", cpu->cfg.ext_svpbmt },
> + { "svinval", cpu->cfg.ext_svinval },
> + { "svnapot", cpu->cfg.ext_svnapot },
> + };
> +
> + for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
> + if (!isa_edata_arr[i].enabled) {
> + continue;
> + }
> + /* check available space */
> + if ((offset + strlen(isa_edata_arr[i].name) + 1) > max_str_len) {
> + qemu_log("No space left to append isa extension");
> + return;
> + }
> + offset += snprintf(isa_str + offset, max_str_len, "_%s",
> + isa_edata_arr[i].name);
> + }
> +}
> +
> char *riscv_isa_string(RISCVCPU *cpu)
> {
> int i;
> - const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
> + const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) +
> + MAX_ISA_EXT_LEN;
> char *isa_str = g_new(char, maxlen);
> char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
> for (i = 0; i < sizeof(riscv_exts); i++) {
> @@ -893,6 +925,7 @@ char *riscv_isa_string(RISCVCPU *cpu)
> }
> }
> *p = '\0';
> + riscv_isa_string_ext(cpu, isa_str, maxlen);
> return isa_str;
> }
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-02-22 22:32 UTC | newest]
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2022-02-16 0:09 [PATCH v2] target/riscv: Add isa extenstion strings to the device tree Atish Patra
2022-02-16 3:18 ` Anup Patel
2022-02-22 22:28 ` Atish Patra
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