How can I know Page Table address on RAM?

How can I know Page Table address on RAM?

[Junho]

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Hello,

I'm a QEMU user with PowerPc target architecture.
I have some personal modifications related to tb jmp cache and chaining
logic to improve the performance of a specific guest code. To verify the
safety, I have to guarantee that the page table on RAM does not change
after initialization. Do you have any information related to this work?
Currently, what I need to find is the page table start address on the RAM
so that I can test with the range detected.

I look forward to your response.

Thank you
Junho

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Re: How can I know Page Table address on RAM?

[Thomas Huth]

On 22/01/2024 05.11, Junho wrote:
> Hello,
> 
> I'm a QEMU user with PowerPc target architecture.
> I have some personal modifications related to tb jmp cache and chaining 
> logic to improve the performance of a specific guest code. To verify the 
> safety, I have to guarantee that the page table on RAM does not change after 
> initialization. Do you have any information related to this work? Currently, 
> what I need to find is the page table start address on the RAM so that I can 
> test with the range detected.
> 
> I look forward to your response.
> 
> Thank you
> Junho

  Hi,

maybe it's best to ask this question on the qemu-ppc mailing list instead 
(done now), since most PPC folks will rather read than one instead of the 
high-traffic qemu-devel mailing list.

  HTH,
   Thomas

Re: How can I know Page Table address on RAM?

[Nicholas Piggin]

On Mon Jan 22, 2024 at 6:54 PM AEST, Thomas Huth wrote:
> On 22/01/2024 05.11, Junho wrote:
> > Hello,
> > 
> > I'm a QEMU user with PowerPc target architecture.
> > I have some personal modifications related to tb jmp cache and chaining 
> > logic to improve the performance of a specific guest code. To verify the 
> > safety, I have to guarantee that the page table on RAM does not change after 
> > initialization. Do you have any information related to this work? Currently, 
> > what I need to find is the page table start address on the RAM so that I can 
> > test with the range detected.
> > 
> > I look forward to your response.
> > 
> > Thank you
> > Junho
>
>   Hi,
>
> maybe it's best to ask this question on the qemu-ppc mailing list instead 
> (done now), since most PPC folks will rather read than one instead of the 
> high-traffic qemu-devel mailing list.

Hi Junho,

ppc targets have a lot of different MMUs, so it depends what you are
looking at.

The hash MMU has a page table that is linear in physical (real) memory,
so you might feasibly be able to watch it for updates. The SDR1 SPR has
hash table base and size. ISA v3.0 and later use an in-memory table
that is pointed to by the PTCR SPR.

Other types are software loaded and radix page tables which might be
infeasible or impossible to really track.

It would be interesting to know what kind of modifications you're doing,
it's possible they might be achieved another way. For example, there is
no requirement in the architecture for the TLB to be kept coherent with
page table modifications, so you might be able to watch for TLB flush
instructions rather than page table changes.

Thanks,
Nick

Re: How can I know Page Table address on RAM?

[Junho]

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Hello Nick,

It helped a lot.
The page table is software loaded on the MMU of the target I'm using.
I'll watch for TLBs as recommended.

Thank you,
Junho



2024년 1월 23일 (화) 오후 4:36, Nicholas Piggin <npiggin@gmail.com>님이 작성:

> On Mon Jan 22, 2024 at 6:54 PM AEST, Thomas Huth wrote:
> > On 22/01/2024 05.11, Junho wrote:
> > > Hello,
> > >
> > > I'm a QEMU user with PowerPc target architecture.
> > > I have some personal modifications related to tb jmp cache and
> chaining
> > > logic to improve the performance of a specific guest code. To verify
> the
> > > safety, I have to guarantee that the page table on RAM does not change
> after
> > > initialization. Do you have any information related to this work?
> Currently,
> > > what I need to find is the page table start address on the RAM so that
> I can
> > > test with the range detected.
> > >
> > > I look forward to your response.
> > >
> > > Thank you
> > > Junho
> >
> >   Hi,
> >
> > maybe it's best to ask this question on the qemu-ppc mailing list
> instead
> > (done now), since most PPC folks will rather read than one instead of
> the
> > high-traffic qemu-devel mailing list.
>
> Hi Junho,
>
> ppc targets have a lot of different MMUs, so it depends what you are
> looking at.
>
> The hash MMU has a page table that is linear in physical (real) memory,
> so you might feasibly be able to watch it for updates. The SDR1 SPR has
> hash table base and size. ISA v3.0 and later use an in-memory table
> that is pointed to by the PTCR SPR.
>
> Other types are software loaded and radix page tables which might be
> infeasible or impossible to really track.
>
> It would be interesting to know what kind of modifications you're doing,
> it's possible they might be achieved another way. For example, there is
> no requirement in the architecture for the TLB to be kept coherent with
> page table modifications, so you might be able to watch for TLB flush
> instructions rather than page table changes.
>
> Thanks,
> Nick
>

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