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From: Richard Henderson <richard.henderson@linaro.org>
To: Philipp Tomsich <philipp.tomsich@vrull.eu>, qemu-devel@nongnu.org
Cc: Kito Cheng <kito.cheng@sifive.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PATCH v3 12/15] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh
Date: Mon, 23 Aug 2021 10:31:31 -0700	[thread overview]
Message-ID: <208618ed-db9b-fcf6-c445-bfc691a66d4b@linaro.org> (raw)
In-Reply-To: <20210823164038.2195113-13-philipp.tomsich@vrull.eu>

On 8/23/21 9:40 AM, Philipp Tomsich wrote:
> The 1.0.0 version of Zbb does not contain pack/packu/packh. However, a
> zext.h instruction is provided (built on pack/packh from pre-0.93
> draft-B) is available.
> 
> This commit adds zext.h and removes the pack* instructions.
> 
> Note that the encodings for zext.h are different between RV32 and
> RV64, which is handled through REQUIRE_32BIT.
> 
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> ---
> 
> Changes in v3:
> - Moved zext.h-addition & pack*-removal to a separate commit.
> 
>   target/riscv/insn32.decode              | 10 +++---
>   target/riscv/insn_trans/trans_rvb.c.inc | 45 +++++++------------------
>   target/riscv/translate.c                | 40 ----------------------
>   3 files changed, 18 insertions(+), 77 deletions(-)
> 
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 72b73c6df2..0fd5afc289 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -689,6 +689,7 @@ rori       01100 ............ 101 ..... 0010011 @sh
>   sext_b     011000 000100 ..... 001 ..... 0010011 @r2
>   sext_h     011000 000101 ..... 001 ..... 0010011 @r2
>   xnor       0100000 .......... 100 ..... 0110011 @r
> +zext_h     0000100 00000 ..... 100 ..... 0110011 @r2

Similarly, I think this should be zext_h_32, and

> @@ -225,6 +207,12 @@ static bool trans_orc_b(DisasContext *ctx, arg_orc_b *a)
>       return gen_unary(ctx, a, &gen_orc_b);
>   }
>   
> +static bool trans_zext_h(DisasContext *ctx, arg_sext_h *a)
> +{
> +    REQUIRE_32BIT(ctx);
> +    REQUIRE_ZBB(ctx);
> +    return gen_unary(ctx, a, &tcg_gen_ext16u_tl);
> +}
>   
>   #define GEN_TRANS_SHADD(SHAMT)                                             \
>   static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
...
> @@ -348,6 +322,13 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
>       return true;
>   }
>   
> +static bool trans_zext_h_64(DisasContext *ctx, arg_sext_h *a)
> +{
> +    REQUIRE_64BIT(ctx);
> +    REQUIRE_ZBB(ctx);
> +    return gen_unary(ctx, a, &tcg_gen_ext16u_tl);
> +}
> +

... the two functions placed together.

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~


  reply	other threads:[~2021-08-23 17:33 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-23 16:40 [PATCH v3 00/15] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
2021-08-23 16:40 ` [PATCH v3 01/15] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties Philipp Tomsich
2021-08-23 16:58   ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 02/15] target/riscv: Reassign instructions to the Zba-extension Philipp Tomsich
2021-08-23 16:59   ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 03/15] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits Philipp Tomsich
2021-08-23 17:02   ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 04/15] target/riscv: Remove the W-form instructions from Zbs Philipp Tomsich
2021-08-23 17:04   ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 05/15] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) Philipp Tomsich
2021-08-23 17:04   ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 06/15] target/riscv: Reassign instructions to the Zbs-extension Philipp Tomsich
2021-08-23 17:07   ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 07/15] target/riscv: Add instructions of the Zbc-extension Philipp Tomsich
2021-08-23 17:17   ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 08/15] target/riscv: Reassign instructions to the Zbb-extension Philipp Tomsich
2021-08-23 17:20   ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 09/15] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci Philipp Tomsich
2021-08-23 17:24   ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 10/15] target/riscv: Add a REQUIRE_32BIT macro Philipp Tomsich
2021-08-23 17:25   ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 11/15] target/riscv: Add rev8 instruction, removing grev/grevi Philipp Tomsich
2021-08-23 17:29   ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 12/15] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh Philipp Tomsich
2021-08-23 17:31   ` Richard Henderson [this message]
2021-08-23 16:40 ` [PATCH v3 13/15] target/riscv: Remove RVB (replaced by Zb[abcs] Philipp Tomsich
2021-08-23 17:33   ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 14/15] target/riscv: rewrite slli.uw implementation to mirror formal spec Philipp Tomsich
2021-08-23 17:36   ` Richard Henderson
2021-08-23 16:40 ` [PATCH v3 15/15] disas/riscv: Add Zb[abcs] instructions Philipp Tomsich

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