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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e37d447sm15173970f8f.4.2025.01.14.09.55.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 14 Jan 2025 09:55:38 -0800 (PST) Message-ID: <20a0768a-38d9-44b5-a050-f893226b5d4e@linaro.org> Date: Tue, 14 Jan 2025 18:55:37 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v2 00/81] tcg: Merge *_i32 and *_i64 opcodes To: Richard Henderson , qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org References: <20250107080112.1175095-1-richard.henderson@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250107080112.1175095-1-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Richard, On 7/1/25 08:59, Richard Henderson wrote: > Currently we have individual opcodes for each integer type. > This makes things difficult in tcg/optimize.c when we want > to transform the opcode stream. > > Add TCGOP_TYPE() and use that instead. Merge the opcodes that are > common to both TCG_TYPE_I32 and TCG_TYPE_I64. We could eventually > merge some of the vector opcodes too, but that is a larger job. > Richard Henderson (81): > tcg: Move call abi parameters from tcg-target.h to tcg-target.c.inc > tcg: Replace TCGOP_VECL with TCGOP_TYPE > tcg: Move tcg_op_insert_{after,before} decls to tcg-internal.h > tcg: Copy TCGOP_TYPE in tcg_op_insert_{after,before} > tcg: Add TCGOP_FLAGS > tcg: Add type and flags arguments to tcg_op_supported > target/arm: Do not test TCG_TARGET_HAS_bitsel_vec > target/arm: Use tcg_op_supported > target/tricore: Use tcg_op_supported > tcg: Add tcg_op_deposit_valid > target/i386: Remove TCG_TARGET_extract_tl_valid > target/i386: Use tcg_op_deposit_valid > target/i386: Use tcg_op_supported > tcg: Remove TCG_TARGET_NEED_LDST_LABELS and > TCG_TARGET_NEED_POOL_LABELS > tcg: Rename tcg-target.opc.h to tcg-target-opc.h.inc > tcg/tci: Move TCI specific opcodes to tcg-target-opc.h.inc > tcg: Move fallback tcg_can_emit_vec_op out of line > tcg: Split out tcg-target-has.h and tcg-has.h > tcg: Split out tcg-target-mo.h > tcg: Use C_NotImplemented in tcg_target_op_def > tcg: Change have_vec to has_type in tcg_op_supported > tcg: Reorg process_op_defs > tcg: Remove args_ct from TCGOpDef > tcg: Constify tcg_op_defs > tcg: Validate op supported in opcode_args_ct > tcg: Add TCG_OPF_NOT_PRESENT to opcodes without inputs or outputs > tcg: Pass type and flags to tcg_target_op_def > tcg: Add TCGType argument to tcg_out_op > tcg: Remove TCG_OPF_64BIT > tcg: Drop implementation checks from tcg-opc.h > tcg: Replace IMPLVEC with TCG_OPF_VECTOR I still have 3 patches to review, but looking at the overall maybe you can merge up to here, as the first part. > tcg/mips: Expand bswap unconditionally (or up to here if I get this one reviewed in time). > tcg/i386: Handle all 8-bit extensions for i686 > tcg/i386: Fold the ext{8,16,32}[us] cases into {s}extract > tcg/aarch64: Provide TCG_TARGET_{s}extract_valid > tcg/aarch64: Expand extract with offset 0 with andi > tcg/arm: Add full [US]XT[BH] into {s}extract > tcg/loongarch64: Fold the ext{8,16,32}[us] cases into {s}extract > tcg/mips: Fold the ext{8,16,32}[us] cases into {s}extract > tcg/ppc: Fold the ext{8,16,32}[us] cases into {s}extract > tcg/riscv64: Fold the ext{8,16,32}[us] cases into {s}extract > tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64 > tcg/s390x: Fold the ext{8,16,32}[us] cases into {s}extract > tcg/sparc64: Use SRA, SRL for {s}extract_i64 > tcg/tci: Provide TCG_TARGET_{s}extract_valid > tcg/tci: Remove assertions for deposit and extract > tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64} > tcg: Remove TCG_TARGET_HAS_deposit_{i32,i64} > tcg: Remove INDEX_op_ext{8,16,32}* > tcg: Add all_outop[] > tcg: Merge INDEX_op_mov_{i32,i64} > tcg: Convert add to TCGOutOpBinary > tcg: Merge INDEX_op_add_{i32,i64} > tcg: Convert and to TCGOutOpBinary > tcg: Merge INDEX_op_and_{i32,i64} > tcg/optimize: Fold andc with immediate to and > tcg/optimize: Emit add r,r,-1 in fold_setcond_tst_pow2 > tcg: Convert andc to TCGOutOpBinary > tcg: Merge INDEX_op_andc_{i32,i64} > tcg: Convert or to TCGOutOpBinary > tcg: Merge INDEX_op_or_{i32,i64} > tcg/optimize: Fold orc with immediate to or > tcg: Convert orc to TCGOutOpBinary > tcg: Merge INDEX_op_orc_{i32,i64} > tcg: Convert xor to TCGOutOpBinary > tcg: Merge INDEX_op_xor_{i32,i64} > tcg/optimize: Fold eqv with immediate to xor > tcg: Convert eqv to TCGOutOpBinary > tcg: Merge INDEX_op_eqv_{i32,i64} > tcg: Convert nand to TCGOutOpBinary > tcg: Merge INDEX_op_nand_{i32,i64} > tcg/loongarch64: Do not accept constant argument to nor > tcg: Convert nor to TCGOutOpBinary > tcg: Merge INDEX_op_nor_{i32,i64} > tcg/arm: Fix constraints for sub > tcg: Convert sub to TCGOutOpSubtract > tcg: Merge INDEX_op_sub_{i32,i64} > tcg: Convert neg to TCGOutOpUnary > tcg: Merge INDEX_op_neg_{i32,i64} > tcg: Convert not to TCGOutOpUnary > tcg: Merge INDEX_op_not_{i32,i64} Here I'm missing the "Convert X to TCGOutOpY" patches. I haven't seen any blocking review difficulty, so will proceed soon. Regards, Phil.