Re: [PATCH v4 0/3] pnv nest1 chiplet model

["Cédric Le Goater" <clg@kaod.org>]

Hello Chalapathi,

Please tune the "From: " email address of the series you send.
This one uses " Chalapathi V <chalap1@gfwr516.rchland.ibm.com>"
which is certainly from an internal IBM host. Unfortunately, we
can not reply to this user/sender.

On 11/7/23 08:41, Chalapathi V wrote:
> From: Chalapathi V <chalapathi.v@linux.ibm.com>
> 
> Hello,
> 
> For modularity reasons the P10 processor chip is split into multiple
> chiplets individually controlled and managed by the pervasive logic.
> The boundaries of these chiplets are defined based on physical design
> parameters like clock grids, the nature of the functional units as well
> as their pervasive requirements (e.g. clock domains). Examples of chiplet
> in the P10 chip are processor cores and caches, memory controllers or IO
> interfaces like PCIe. Partitioning the processor chip into these chiplets
> allows the pervasive logic to test, initialize, control and manage these
> chip partitions individually.
> 
> In this series, we create a nest1 chiplet model and implements the chiplet
> control scom registers on nest1 chiplet. The chiplet control registers does
> the initialization and configuration of a chiplet.
> 
> PATCH4: The review comments of PATCH3 has been addressed.

What do you mean by PATCH4 and PATCH3 ? Version 4 and 3 ?

Usually, people send a small changelog with the cover letter explaining
the differences between each respin. See the Zhenzhong's series "vfio:
Adopt iommufd" [1] for an example. Your series does not need that much
details, but "comments have been addressed" is not very useful.

Thanks,

C.


> 
> /nest1_chiplet (pnv-nest1-chiplet)
>        /perv_chiplet (pnv-pervasive-chiplet)
>          /xscom-chiplet-control-regs[0] (memory-region)
> 
> Chalapathi V (3):
>    hw/ppc: Add pnv pervasive common chiplet units
>    hw/ppc: Add nest1 chiplet model
>    hw/ppc: Nest1 chiplet wiring
> 
>   hw/ppc/meson.build                |   2 +
>   hw/ppc/pnv.c                      |  14 +++
>   hw/ppc/pnv_nest1_chiplet.c        |  94 +++++++++++++++++
>   hw/ppc/pnv_pervasive.c            | 213 ++++++++++++++++++++++++++++++++++++++
>   include/hw/ppc/pnv_chip.h         |   2 +
>   include/hw/ppc/pnv_nest_chiplet.h |  41 ++++++++
>   include/hw/ppc/pnv_pervasive.h    |  39 +++++++
>   include/hw/ppc/pnv_xscom.h        |   3 +
>   8 files changed, 408 insertions(+)
>   create mode 100644 hw/ppc/pnv_nest1_chiplet.c
>   create mode 100644 hw/ppc/pnv_pervasive.c
>   create mode 100644 include/hw/ppc/pnv_nest_chiplet.h
>   create mode 100644 include/hw/ppc/pnv_pervasive.h
>