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Thu, 19 Sep 2024 03:04:38 -0700 (PDT) Message-ID: <20e20fde-830f-4314-a944-e7973bda5d8c@linaro.org> Date: Wed, 18 Sep 2024 16:27:16 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 02/12] tcg/riscv: Add basic support for vector To: LIU Zhiwei , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, Swung0x48 , TANG Tiancheng References: <20240911132630.461-1-zhiwei_liu@linux.alibaba.com> <20240911132630.461-3-zhiwei_liu@linux.alibaba.com> <0d591570-02c6-48c9-9e3f-ef47ac20ce7d@linaro.org> <33101e38-080d-4444-a8c3-9d01827e243f@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_12_24=1.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/18/24 12:43, LIU Zhiwei wrote: > > On 2024/9/18 18:11, Richard Henderson wrote: >> On 9/18/24 07:17, LIU Zhiwei wrote: >>> >>> On 2024/9/12 2:41, Richard Henderson wrote: >>>> On 9/11/24 06:26, LIU Zhiwei wrote: >>>>> From: Swung0x48 >>>>> >>>>> The RISC-V vector instruction set utilizes the LMUL field to group >>>>> multiple registers, enabling variable-length vector registers. This >>>>> implementation uses only the first register number of each group while >>>>> reserving the other register numbers within the group. >>>>> >>>>> In TCG, each VEC_IR can have 3 types (TCG_TYPE_V64/128/256), and the >>>>> host runtime needs to adjust LMUL based on the type to use different >>>>> register groups. >>>>> >>>>> This presents challenges for TCG's register allocation. Currently, we >>>>> avoid modifying the register allocation part of TCG and only expose the >>>>> minimum number of vector registers. >>>>> >>>>> For example, when the host vlen is 64 bits and type is TCG_TYPE_V256, with >>>>> LMUL equal to 4, we use 4 vector registers as one register group. We can >>>>> use a maximum of 8 register groups, but the V0 register number is reserved >>>>> as a mask register, so we can effectively use at most 7 register groups. >>>>> Moreover, when type is smaller than TCG_TYPE_V256, only 7 registers are >>>>> forced to be used. This is because TCG cannot yet dynamically constrain >>>>> registers with type; likewise, when the host vlen is 128 bits and >>>>> TCG_TYPE_V256, we can use at most 15 registers. >>>>> >>>>> There is not much pressure on vector register allocation in TCG now, so >>>>> using 7 registers is feasible and will not have a major impact on code >>>>> generation. >>>>> >>>>> This patch: >>>>> 1. Reserves vector register 0 for use as a mask register. >>>>> 2. When using register groups, reserves the additional registers within >>>>>     each group. >>>>> >>>>> Signed-off-by: TANG Tiancheng >>>>> Co-authored-by: TANG Tiancheng >>>> >>>> If there is a co-author, there should be another Signed-off-by. >>> >>> This patch has added a tag: >>> >>> Signed-off-by: TANG Tiancheng >>> >>> >>> Do you mean we should add the same tag twice? >> >> The from line is "Swung0x48 ". >> If this is an alternate email for TANG Tiancheng, > > No, Swung0x48 is another author. Then we need a proper Signed-off-by line from that author. r~