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From: Farhan Ali <alifm@linux.ibm.com>
To: Stefan Hajnoczi <stefanha@redhat.com>
Cc: qemu-devel@nongnu.org, mjrosato@linux.ibm.com,
	schnelle@linux.ibm.com, qemu-block@nongnu.org,
	qemu-s390x@nongnu.org, fam@euphon.net, philmd@linaro.org,
	kwolf@redhat.com, hreitz@redhat.com, thuth@redhat.com
Subject: Re: [PATCH v2 2/3] include: Add a header to define PCI MMIO functions
Date: Tue, 1 Apr 2025 06:02:30 -0700	[thread overview]
Message-ID: <20f92b8e-969f-4a0a-a2c8-62fe95b88690@linux.ibm.com> (raw)
In-Reply-To: <20250331134656.GC190936@fedora>


On 3/31/2025 6:46 AM, Stefan Hajnoczi wrote:
> On Fri, Mar 28, 2025 at 12:06:26PM -0700, Farhan Ali wrote:
>> Add a generic QEMU API for PCI MMIO reads/writes.
>> The functions access little endian memory and returns
>> the result in host cpu endianness.
>>
>> Signed-off-by: Farhan Ali <alifm@linux.ibm.com>
>> ---
>>   include/qemu/pci-mmio.h | 116 ++++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 116 insertions(+)
>>   create mode 100644 include/qemu/pci-mmio.h
>>
>> diff --git a/include/qemu/pci-mmio.h b/include/qemu/pci-mmio.h
>> new file mode 100644
>> index 0000000000..2ef92455b1
>> --- /dev/null
>> +++ b/include/qemu/pci-mmio.h
>> @@ -0,0 +1,116 @@
>> +/*
>> + * QEMU PCI MMIO API
> QEMU also emulates PCI devices that handle MMIO accesses. It is easy to
> get confused between host PCI MMIO accesses and emulated guest PCI MMIO
> accesses if the name is just "PCI MMIO API".
>
> Please update the commit message, filenames, function names, and doc
> comments to make it clear that this is only for host PCI MMIO accesses
> (e.g. Linux VFIO BAR accesses).
>
> For example "qemu/host-pci-mmio.h", "API for host PCI MMIO accesses
> (e.g. Linux VFIO BARs)", and host_pci_mmio_read_8().

yeah this makes sense. Will update the API names in v3.


>> + *
>> + * Copyright 2025 IBM Corp.
>> + * Author(s): Farhan Ali <alifm@linux.ibm.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0-or-later
>> + */
>> +
>> +#ifndef QEMU_PCI_MMIO_H
>> +#define QEMU_PCI_MMIO_H
>> +
>> +#ifdef __s390x__
>> +#include "s390x_pci_mmio.h"
>> +#endif
>> +
>> +static inline uint8_t qemu_pci_mmio_read_8(const void *ioaddr)
>> +{
>> +    uint8_t ret = 0;
>> +#ifdef __s390x__
>> +    ret = s390x_pci_mmio_read_8(ioaddr);
>> +#else
>> +    /* Prevent the compiler from optimizing away the load */
>> +    ret = *((volatile uint8_t *)ioaddr);
>> +#endif
>> +
>> +    return ret;
>> +}
>> +
>> +static inline uint16_t qemu_pci_mmio_read_16(const void *ioaddr)
>> +{
>> +    uint16_t ret = 0;
>> +#ifdef __s390x__
>> +    ret = s390x_pci_mmio_read_16(ioaddr);
>> +#else
>> +    /* Prevent the compiler from optimizing away the load */
>> +    ret = *((volatile uint16_t *)ioaddr);
>> +#endif
>> +
>> +    return le16_to_cpu(ret);
>> +}
>> +
>> +static inline uint32_t qemu_pci_mmio_read_32(const void *ioaddr)
>> +{
>> +    uint32_t ret = 0;
>> +#ifdef __s390x__
>> +    ret = s390x_pci_mmio_read_32(ioaddr);
>> +#else
>> +    /* Prevent the compiler from optimizing away the load */
>> +    ret = *((volatile uint32_t *)ioaddr);
>> +#endif
>> +
>> +    return le32_to_cpu(ret);
>> +}
>> +
>> +static inline uint64_t qemu_pci_mmio_read_64(const void *ioaddr)
>> +{
>> +    uint64_t ret = 0;
>> +#ifdef __s390x__
>> +    ret = s390x_pci_mmio_read_64(ioaddr);
>> +#else
>> +    /* Prevent the compiler from optimizing away the load */
>> +    ret = *((volatile uint64_t *)ioaddr);
>> +#endif
>> +
>> +    return le64_to_cpu(ret);
>> +}
>> +
>> +static inline void qemu_pci_mmio_write_8(void *ioaddr, uint8_t val)
>> +{
>> +
>> +#ifdef __s390x__
>> +    s390x_pci_mmio_write_8(ioaddr, val);
>> +#else
>> +    /* Prevent the compiler from optimizing away the store */
>> +    *((volatile uint8_t *)ioaddr) = val;
>> +#endif
>> +}
>> +
>> +static inline void qemu_pci_mmio_write_16(void *ioaddr, uint16_t val)
>> +{
>> +    val = cpu_to_le16(val);
>> +
>> +#ifdef __s390x__
>> +    s390x_pci_mmio_write_16(ioaddr, val);
>> +#else
>> +    /* Prevent the compiler from optimizing away the store */
>> +    *((volatile uint16_t *)ioaddr) = val;
>> +#endif
>> +}
>> +
>> +static inline void qemu_pci_mmio_write_32(void *ioaddr, uint32_t val)
>> +{
>> +    val = cpu_to_le32(val);
>> +
>> +#ifdef __s390x__
>> +    s390x_pci_mmio_write_32(ioaddr, val);
>> +#else
>> +    /* Prevent the compiler from optimizing away the store */
>> +    *((volatile uint32_t *)ioaddr) = val;
>> +#endif
>> +}
>> +
>> +static inline void qemu_pci_mmio_write_64(void *ioaddr, uint64_t val)
>> +{
>> +    val = cpu_to_le64(val);
>> +
>> +#ifdef __s390x__
>> +    s390x_pci_mmio_write_64(ioaddr, val);
>> +#else
>> +    /* Prevent the compiler from optimizing away the store */
>> +    *((volatile uint64_t *)ioaddr) = val;
>> +#endif
>> +}
>> +
>> +#endif
>> -- 
>> 2.43.0
>>


  reply	other threads:[~2025-04-01 13:04 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-28 19:06 [PATCH v2 0/3] Enable QEMU NVMe userspace driver on s390x Farhan Ali
2025-03-28 19:06 ` [PATCH v2 1/3] util: Add functions for s390x mmio read/write Farhan Ali
2025-03-31  7:34   ` Niklas Schnelle
2025-03-28 19:06 ` [PATCH v2 2/3] include: Add a header to define PCI MMIO functions Farhan Ali
2025-03-28 20:38   ` Philippe Mathieu-Daudé
2025-03-29  5:58     ` Farhan Ali
2025-03-28 20:44   ` Philippe Mathieu-Daudé
2025-03-29  6:03     ` Farhan Ali
2025-03-29  6:50       ` Philippe Mathieu-Daudé
2025-03-31 13:46   ` Stefan Hajnoczi
2025-04-01 13:02     ` Farhan Ali [this message]
2025-03-28 19:06 ` [PATCH v2 3/3] block/nvme: Use QEMU PCI MMIO API Farhan Ali
2025-03-28 20:41   ` Philippe Mathieu-Daudé
2025-03-29  6:04     ` Farhan Ali
2025-03-31 16:58   ` Stefan Hajnoczi

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