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[200.162.225.121]) by smtp.gmail.com with ESMTPSA id ec11-20020a0568708c0b00b001964cb38d37sm2978489oab.11.2023.05.27.11.03.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 27 May 2023 11:04:00 -0700 (PDT) Message-ID: <212ab1d7-c902-9675-9267-aae6d549556c@gmail.com> Date: Sat, 27 May 2023 15:03:58 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH] target/ppc: Use SMT4 small core chip type in POWER9/10 PVRs Content-Language: en-US To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, Harsh Prateek Bora References: <20230515160131.394562-1-npiggin@gmail.com> From: Daniel Henrique Barboza In-Reply-To: <20230515160131.394562-1-npiggin@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c2d; envelope-from=danielhb413@gmail.com; helo=mail-oo1-xc2d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, NICE_REPLY_A=-0.091, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/15/23 13:01, Nicholas Piggin wrote: > QEMU's PVR value for POWER9 DD2.0 has chip type 1, which is the SMT4 > "small core" type that OpenPOWER processors use. QEMU's PVR for all > other POWER9/10 have chip type 0, which "enterprise" systems use. > > The difference does not really matter to QEMU (because it does not care > about SMT mode in the target), but for consistency all PVRs should use > the same chip type. We'll go with the SMT4 OpenPOWER type. > > Signed-off-by: Nicholas Piggin > --- Reviewed-by: Daniel Henrique Barboza And queued. Thanks, Daniel > This is a replacement for > > https://lists.gnu.org/archive/html/qemu-ppc/2022-03/msg00227.html > > But the chip type is changed to 1 instead of 0, because that's the > more familiar SM4 / small core CPU. > > Thanks, > Nick > > target/ppc/cpu-models.h | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h > index 1326493a9a..a77e036b3a 100644 > --- a/target/ppc/cpu-models.h > +++ b/target/ppc/cpu-models.h > @@ -348,11 +348,11 @@ enum { > CPU_POWERPC_POWER8NVL_BASE = 0x004C0000, > CPU_POWERPC_POWER8NVL_v10 = 0x004C0100, > CPU_POWERPC_POWER9_BASE = 0x004E0000, > - CPU_POWERPC_POWER9_DD1 = 0x004E0100, > + CPU_POWERPC_POWER9_DD1 = 0x004E1100, > CPU_POWERPC_POWER9_DD20 = 0x004E1200, > CPU_POWERPC_POWER10_BASE = 0x00800000, > - CPU_POWERPC_POWER10_DD1 = 0x00800100, > - CPU_POWERPC_POWER10_DD20 = 0x00800200, > + CPU_POWERPC_POWER10_DD1 = 0x00801100, > + CPU_POWERPC_POWER10_DD20 = 0x00801200, > CPU_POWERPC_970_v22 = 0x00390202, > CPU_POWERPC_970FX_v10 = 0x00391100, > CPU_POWERPC_970FX_v20 = 0x003C0200,