From: Thomas Huth <thuth@redhat.com>
To: Paolo Bonzini <pbonzini@redhat.com>, qemu-devel@nongnu.org
Cc: qemu-stable@nongnu.org
Subject: Re: [PATCH] target/i386: fix access to the T bit of the TSS
Date: Mon, 13 Oct 2025 18:15:03 +0200 [thread overview]
Message-ID: <2151ff2f-e965-47b5-9505-1ba2382f9f45@redhat.com> (raw)
In-Reply-To: <20251013161152.992880-1-pbonzini@redhat.com>
On 13/10/2025 18.11, Paolo Bonzini wrote:
> The T bit is bit 0 of the 16-bit word at offset 100 of the TSS. However,
> accessing it with a 32-bit word is not really correct, because bytes
> 102-103 contain the I/O map base address (relative to the base of the
> TSS) and bits 1-15 are reserved. In particular, any task switch to a TSS that
> has a nonzero I/O map base address is broken.
>
> This fixes the eventinj and taskswitch tests in kvm-unit-tests.
>
> Cc: qemu-stable@nongnu.org
> Fixes: ad441b8b791 ("target/i386: implement TSS trap bit", 2025-05-12)
> Reported-by: Thomas Huth <thuth@redhat.com>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Closes: https://gitlab.com/qemu-project/qemu/-/issues/3101
Tested-by: Thomas Huth <thuth@redhat.com>
prev parent reply other threads:[~2025-10-13 16:15 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-13 16:11 [PATCH] target/i386: fix access to the T bit of the TSS Paolo Bonzini
2025-10-13 16:15 ` Thomas Huth [this message]
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