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[174.21.75.75]) by smtp.gmail.com with ESMTPSA id t12sm21388pjo.44.2021.12.13.12.46.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 13 Dec 2021 12:46:33 -0800 (PST) Subject: Re: [PATCH] Target/arm: Implement Cortex-A5 To: Byron Lathi , qemu-devel@nongnu.org References: <20211213182449.7068-1-bslathi19@gmail.com> From: Richard Henderson Message-ID: <215c98d7-2be4-56d3-7487-ebb7472be17c@linaro.org> Date: Mon, 13 Dec 2021 12:46:32 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: <20211213182449.7068-1-bslathi19@gmail.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102c (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -53 X-Spam_score: -5.4 X-Spam_bar: ----- X-Spam_report: (-5.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-4.093, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/13/21 10:24 AM, Byron Lathi wrote: > Add support for the Cortex-A5. These changes are based off of the A7 and > A9 init functions, using the appropriate values from the technical > reference manual for the A5. > > Signed-off-by: Byron Lathi > --- > target/arm/cpu_tcg.c | 37 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c > index 13d0e9b195..38f0fc3977 100644 > --- a/target/arm/cpu_tcg.c > +++ b/target/arm/cpu_tcg.c > @@ -304,6 +304,42 @@ static void cortex_a8_initfn(Object *obj) > define_arm_cp_regs(cpu, cortexa8_cp_reginfo); > } > > +static void cortex_a5_initfn(Object *obj) > +{ > + ARMCPU *cpu = ARM_CPU(obj); > + > + cpu->dtb_compatible = "arm,cortex-a5"; > + set_feature(&cpu->env, ARM_FEATURE_V7); > + set_feature(&cpu->env, ARM_FEATURE_NEON); > + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); > + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); > + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); > + set_feature(&cpu->env, ARM_FEATURE_PMU); > + cpu->midr = 0x410fc0f1; > + cpu->reset_fpsid = 0x41023051; > + cpu->isar.mvfr0 = 0x10110221; > + cpu->isar.mvfr1 = 0x11000011; > + cpu->ctr = 0x83338003; > + cpu->reset_sctlr = 0x00c50078; > + cpu->isar.id_pfr0 = 0x00001231; > + cpu->isar.id_pfr1 = 0x00000011; > + cpu->isar.id_dfr0 = 0x02010444; > + cpu->id_afr0 = 0x00000000; > + cpu->isar.id_mmfr0 = 0x00100103; > + cpu->isar.id_mmfr1 = 0x40000000; > + cpu->isar.id_mmfr2 = 0x01230000; > + cpu->isar.id_mmfr3 = 0x00102211; > + cpu->isar.id_isar0 = 0x00101111; > + cpu->isar.id_isar1 = 0x13112111; > + cpu->isar.id_isar2 = 0x21232041; > + cpu->isar.id_isar3 = 0x11112131; > + cpu->isar.id_isar4 = 0x00011142; > + cpu->isar.dbgdidr = 0x1203f001; > + cpu->clidr = 0x09200003; > + cpu->ccsidr[0] = 0x701fe00a; > + cpu->ccsidr[1] = 0x203fe00a; > +} Looks ok. > + { .name = "cortext-a5", .initfn = cortex_a5_initfn }, Typo. In addition, you probably want to add the cortex-a5 to the list of cpus that are supported by hw/arm/virt.c, and then you need to add this to docs/system/arm/virt.rst. r~