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Wed, 14 May 2025 19:48:03 +0000 (GMT) Message-ID: <216b782e-d90f-435e-8111-422288da6864@linux.ibm.com> Date: Wed, 14 May 2025 14:48:03 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 25/50] ppc/xive2: Implement "Ack OS IRQ to even report line" TIMA op To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, =?UTF-8?B?RnLDqWTDqXJpYyBCYXJyYXQ=?= , Glenn Miles , Caleb Schlossin References: <20250512031100.439842-1-npiggin@gmail.com> <20250512031100.439842-26-npiggin@gmail.com> Content-Language: en-US From: Mike Kowal In-Reply-To: <20250512031100.439842-26-npiggin@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=IqAecK/g c=1 sm=1 tr=0 ts=6824f377 cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=VnNF1IyMAAAA:8 a=o8TdU-I3RdqAkSISKskA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-ORIG-GUID: -q2RyWiOALCrmP8zfjJ5wPgQJ71NGQQD X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE0MDE4MCBTYWx0ZWRfX6EALJtVvQVas uTUHkOW+I9uLlDk3in2XzllKlftpdJwFhqhNcE6LfG0jykH8Hc2Pqxeye/1OxGTTuJIe/XU08mG vgvQIgCP0Folce2qc8ao+T/tp6W1w3y/gyDiN+0xOlbK7Yin1Wz7DEu123pcb2Jj16efT5O76mu ag43CP4PrsdxBp/cHd7v+ML48foMSEjmLrRnPiWR1bUYB2eKgow+Y5/47phW+lhfEqSUgg+kQBu 0aNpfwYpcj782l+VOLmg4k+Uzyw2OdRhxHbvvYmokq8g3aEeuJtCNmbcb6huoFc3cNYyC8Zrj8p OQTNmp+irb02sGc5hDRDkhMJ8TElSZRCaWeFCXP5utU4nG7drZLqV/JOJCfhNUgvD2uUlx2jUiz fhu1uj5PR2cEssoo9pYv6OOr7vLXT6vzdCSZFMNjGAuRI3eywuloKYqoDnNyl6vLHOvcRjIV X-Proofpoint-GUID: InW5hARvU8w3t3Hw8gTvAAxcQjSouRdm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-14_04,2025-05-14_03,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 priorityscore=1501 clxscore=1015 spamscore=0 mlxlogscore=999 bulkscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505140180 Received-SPF: pass client-ip=148.163.158.5; envelope-from=kowal@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/11/2025 10:10 PM, Nicholas Piggin wrote: > From: Glenn Miles > > Booting AIX in a PowerVM partition requires the use of the "Acknowledge > O/S Interrupt to even O/S reporting line" special operation provided by > the IBM XIVE interrupt controller. This operation is invoked by writing > a byte (data is irrelevant) to offset 0xC10 of the Thread Interrupt > Management Area (TIMA). It can be used by software to notify the XIVE > logic that the interrupt was received. Reviewed-by: Michael Kowal Thanks, MAK > > Signed-off-by: Glenn Miles > --- > hw/intc/xive.c | 8 ++++--- > hw/intc/xive2.c | 50 ++++++++++++++++++++++++++++++++++++++++++ > include/hw/ppc/xive.h | 1 + > include/hw/ppc/xive2.h | 3 ++- > 4 files changed, 58 insertions(+), 4 deletions(-) > > diff --git a/hw/intc/xive.c b/hw/intc/xive.c > index 7461dbecb8..9ec1193dfc 100644 > --- a/hw/intc/xive.c > +++ b/hw/intc/xive.c > @@ -80,7 +80,7 @@ static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t ring) > } > } > > -static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) > +uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) > { > uint8_t *regs = &tctx->regs[ring]; > uint8_t nsr = regs[TM_NSR]; > @@ -340,14 +340,14 @@ static uint64_t xive_tm_vt_poll(XivePresenter *xptr, XiveTCTX *tctx, > > static const uint8_t xive_tm_hw_view[] = { > 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ > - 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ > + 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 3, /* QW-1 OS */ > 0, 0, 3, 3, 0, 3, 3, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ > 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */ > }; > > static const uint8_t xive_tm_hv_view[] = { > 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ > - 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ > + 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 3, /* QW-1 OS */ > 0, 0, 3, 3, 0, 3, 3, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ > 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */ > }; > @@ -718,6 +718,8 @@ static const XiveTmOp xive2_tm_operations[] = { > xive_tm_pull_phys_ctx }, > { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_OL, 1, xive2_tm_pull_phys_ctx_ol, > NULL }, > + { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_EL, 1, xive2_tm_ack_os_el, > + NULL }, > }; > > static const XiveTmOp *xive_tm_find_op(XivePresenter *xptr, hwaddr offset, > diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c > index ec4b9320b4..68be138335 100644 > --- a/hw/intc/xive2.c > +++ b/hw/intc/xive2.c > @@ -1009,6 +1009,56 @@ static int xive2_tctx_get_nvp_indexes(XiveTCTX *tctx, uint8_t ring, > return 0; > } > > +static void xive2_tctx_accept_el(XivePresenter *xptr, XiveTCTX *tctx, > + uint8_t ring, uint8_t cl_ring) > +{ > + uint64_t rd; > + Xive2Router *xrtr = XIVE2_ROUTER(xptr); > + uint32_t nvp_blk, nvp_idx, xive2_cfg; > + Xive2Nvp nvp; > + uint64_t phys_addr; > + uint8_t OGen = 0; > + > + xive2_tctx_get_nvp_indexes(tctx, cl_ring, &nvp_blk, &nvp_idx); > + > + if (xive2_router_get_nvp(xrtr, (uint8_t)nvp_blk, nvp_idx, &nvp)) { > + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", > + nvp_blk, nvp_idx); > + return; > + } > + > + if (!xive2_nvp_is_valid(&nvp)) { > + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", > + nvp_blk, nvp_idx); > + return; > + } > + > + > + rd = xive_tctx_accept(tctx, ring); > + > + if (ring == TM_QW1_OS) { > + OGen = tctx->regs[ring + TM_OGEN]; > + } > + xive2_cfg = xive2_router_get_config(xrtr); > + phys_addr = xive2_nvp_reporting_addr(&nvp); > + uint8_t report_data[REPORT_LINE_GEN1_SIZE]; > + memset(report_data, 0xff, sizeof(report_data)); > + if ((OGen == 1) || (xive2_cfg & XIVE2_GEN1_TIMA_OS)) { > + report_data[8] = (rd >> 8) & 0xff; > + report_data[9] = rd & 0xff; > + } else { > + report_data[0] = (rd >> 8) & 0xff; > + report_data[1] = rd & 0xff; > + } > + cpu_physical_memory_write(phys_addr, report_data, REPORT_LINE_GEN1_SIZE); > +} > + > +void xive2_tm_ack_os_el(XivePresenter *xptr, XiveTCTX *tctx, > + hwaddr offset, uint64_t value, unsigned size) > +{ > + xive2_tctx_accept_el(xptr, tctx, TM_QW1_OS, TM_QW1_OS); > +} > + > static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) > { > uint8_t *regs = &tctx->regs[ring]; > diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h > index 28f0f1b79a..46d05d74fb 100644 > --- a/include/hw/ppc/xive.h > +++ b/include/hw/ppc/xive.h > @@ -561,6 +561,7 @@ void xive_tctx_pipr_update(XiveTCTX *tctx, uint8_t ring, uint8_t priority, > uint8_t group_level); > void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t ring); > void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring, uint8_t group_level); > +uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring); > > /* > * KVM XIVE device helpers > diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h > index 760b94a962..ff02ce2549 100644 > --- a/include/hw/ppc/xive2.h > +++ b/include/hw/ppc/xive2.h > @@ -142,5 +142,6 @@ void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx, > hwaddr offset, uint64_t value, unsigned size); > void xive2_tm_pull_phys_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, > hwaddr offset, uint64_t value, unsigned size); > - > +void xive2_tm_ack_os_el(XivePresenter *xptr, XiveTCTX *tctx, > + hwaddr offset, uint64_t value, unsigned size); > #endif /* PPC_XIVE2_H */