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From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
To: qemu-devel@nongnu.org
Cc: philmd@linaro.org,
	Richard Henderson <richard.henderson@linaro.org>,
	Yannis Bolliger <yannis.bolliger@protonmail.com>,
	qemu-arm@nongnu.org, alex.bennee@linaro.org,
	Paolo Bonzini <pbonzini@redhat.com>,
	Peter Maydell <peter.maydell@linaro.org>
Subject: Re: [PATCH v2 0/4] target/arm: fix arm_cpu_get_phys_page_attrs_debug
Date: Mon, 28 Apr 2025 12:34:21 -0700	[thread overview]
Message-ID: <21843e8d-cdbc-4f84-a652-01ee467f2dc7@linaro.org> (raw)
In-Reply-To: <20250414153027.1486719-1-pierrick.bouvier@linaro.org>

On 4/14/25 8:30 AM, Pierrick Bouvier wrote:
> It was reported that QEMU monitor command gva2gpa was reporting unmapped
> memory for a valid access (qemu-system-aarch64), during a copy from
> kernel to user space (__arch_copy_to_user symbol in Linux) [1].
> This was affecting cpu_memory_rw_debug also, which
> is used in numerous places in our codebase. After investigating, the
> problem was specific to arm_cpu_get_phys_page_attrs_debug.
> 
> [1] https://lists.nongnu.org/archive/html/qemu-discuss/2025-04/msg00013.html
> 
> When performing user access from a privileged space, we need to do a
> second lookup for user mmu idx, following what get_a64_user_mem_index is
> doing at translation time.
> 
> This series first extract some functions, and then perform the second lookup
> expected using extracted functions.
> 
> Besides running all QEMU tests, it was explicitely checked that during a linux
> boot sequence, accesses now report a valid physical address inconditionnally
> using this (non sent) patch:
> 
> --- a/accel/tcg/cputlb.c
> +++ b/accel/tcg/cputlb.c
> @@ -997,9 +997,7 @@ static inline void tlb_set_compare(CPUTLBEntryFull *full, CPUTLBEntry *ent,
>       if (enable) {
>           address |= flags & TLB_FLAGS_MASK;
>           flags &= TLB_SLOW_FLAGS_MASK;
> -        if (flags) {
>               address |= TLB_FORCE_SLOW;
> -        }
>       } else {
>           address = -1;
>           flags = 0;
> @@ -1658,6 +1656,10 @@ static bool mmu_lookup1(CPUState *cpu, MMULookupPageData *data, MemOp memop,
>           tlb_addr = tlb_read_idx(entry, access_type) & ~TLB_INVALID_MASK;
>       }
> 
> +    vaddr page = addr & TARGET_PAGE_MASK;
> +    hwaddr physaddr = cpu_get_phys_page_debug(cpu, page);
> +    g_assert(physaddr != -1);
> +
>       full = &cpu->neg.tlb.d[mmu_idx].fulltlb[index];
>       flags = tlb_addr & (TLB_FLAGS_MASK & ~TLB_FORCE_SLOW);
>       flags |= full->slow_flags[access_type];
> 
> v2:
> - fix style in first commit (philmd)
> 
> Pierrick Bouvier (4):
>    target/arm/ptw: extract arm_mmu_idx_to_security_space
>    target/arm/ptw: get current security_space for current mmu_idx
>    target/arm/ptw: extract arm_cpu_get_phys_page
>    target/arm/ptw: fix arm_cpu_get_phys_page_attrs_debug
> 
>   target/arm/ptw.c | 65 +++++++++++++++++++++++++++++++++++-------------
>   1 file changed, 48 insertions(+), 17 deletions(-)
> 

Gentle ping on this series.
Any plan to queue it to tcg-next @Richard?

Regards,
Pierrick


  parent reply	other threads:[~2025-04-28 19:35 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-14 15:30 [PATCH v2 0/4] target/arm: fix arm_cpu_get_phys_page_attrs_debug Pierrick Bouvier
2025-04-14 15:30 ` [PATCH v2 1/4] target/arm/ptw: extract arm_mmu_idx_to_security_space Pierrick Bouvier
2025-04-14 15:30 ` [PATCH v2 2/4] target/arm/ptw: get current security_space for current mmu_idx Pierrick Bouvier
2025-04-14 15:30 ` [PATCH v2 3/4] target/arm/ptw: extract arm_cpu_get_phys_page Pierrick Bouvier
2025-04-14 15:30 ` [PATCH v2 4/4] target/arm/ptw: fix arm_cpu_get_phys_page_attrs_debug Pierrick Bouvier
2025-04-28 19:34 ` Pierrick Bouvier [this message]
2025-05-02 13:05   ` [PATCH v2 0/4] target/arm: " Peter Maydell
2025-05-02 16:13     ` Pierrick Bouvier

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