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Mon, 28 Apr 2025 12:34:22 -0700 (PDT) Received: from [192.168.1.87] ([38.41.223.211]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73e25914238sm8435744b3a.7.2025.04.28.12.34.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Apr 2025 12:34:21 -0700 (PDT) Message-ID: <21843e8d-cdbc-4f84-a652-01ee467f2dc7@linaro.org> Date: Mon, 28 Apr 2025 12:34:21 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 0/4] target/arm: fix arm_cpu_get_phys_page_attrs_debug Content-Language: en-US To: qemu-devel@nongnu.org Cc: philmd@linaro.org, Richard Henderson , Yannis Bolliger , qemu-arm@nongnu.org, alex.bennee@linaro.org, Paolo Bonzini , Peter Maydell References: <20250414153027.1486719-1-pierrick.bouvier@linaro.org> From: Pierrick Bouvier In-Reply-To: <20250414153027.1486719-1-pierrick.bouvier@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 4/14/25 8:30 AM, Pierrick Bouvier wrote: > It was reported that QEMU monitor command gva2gpa was reporting unmapped > memory for a valid access (qemu-system-aarch64), during a copy from > kernel to user space (__arch_copy_to_user symbol in Linux) [1]. > This was affecting cpu_memory_rw_debug also, which > is used in numerous places in our codebase. After investigating, the > problem was specific to arm_cpu_get_phys_page_attrs_debug. > > [1] https://lists.nongnu.org/archive/html/qemu-discuss/2025-04/msg00013.html > > When performing user access from a privileged space, we need to do a > second lookup for user mmu idx, following what get_a64_user_mem_index is > doing at translation time. > > This series first extract some functions, and then perform the second lookup > expected using extracted functions. > > Besides running all QEMU tests, it was explicitely checked that during a linux > boot sequence, accesses now report a valid physical address inconditionnally > using this (non sent) patch: > > --- a/accel/tcg/cputlb.c > +++ b/accel/tcg/cputlb.c > @@ -997,9 +997,7 @@ static inline void tlb_set_compare(CPUTLBEntryFull *full, CPUTLBEntry *ent, > if (enable) { > address |= flags & TLB_FLAGS_MASK; > flags &= TLB_SLOW_FLAGS_MASK; > - if (flags) { > address |= TLB_FORCE_SLOW; > - } > } else { > address = -1; > flags = 0; > @@ -1658,6 +1656,10 @@ static bool mmu_lookup1(CPUState *cpu, MMULookupPageData *data, MemOp memop, > tlb_addr = tlb_read_idx(entry, access_type) & ~TLB_INVALID_MASK; > } > > + vaddr page = addr & TARGET_PAGE_MASK; > + hwaddr physaddr = cpu_get_phys_page_debug(cpu, page); > + g_assert(physaddr != -1); > + > full = &cpu->neg.tlb.d[mmu_idx].fulltlb[index]; > flags = tlb_addr & (TLB_FLAGS_MASK & ~TLB_FORCE_SLOW); > flags |= full->slow_flags[access_type]; > > v2: > - fix style in first commit (philmd) > > Pierrick Bouvier (4): > target/arm/ptw: extract arm_mmu_idx_to_security_space > target/arm/ptw: get current security_space for current mmu_idx > target/arm/ptw: extract arm_cpu_get_phys_page > target/arm/ptw: fix arm_cpu_get_phys_page_attrs_debug > > target/arm/ptw.c | 65 +++++++++++++++++++++++++++++++++++------------- > 1 file changed, 48 insertions(+), 17 deletions(-) > Gentle ping on this series. Any plan to queue it to tcg-next @Richard? Regards, Pierrick