From: WANG Xuerui <i.qemu@xen0n.name>
To: Richard Henderson <richard.henderson@linaro.org>,
qemu-devel <qemu-devel@nongnu.org>
Subject: Re: [PATCH v3 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi
Date: Sat, 25 Sep 2021 00:26:26 +0800 [thread overview]
Message-ID: <21860285-7cec-28a7-0c01-5ab244d562ab@xen0n.name> (raw)
In-Reply-To: <26730e70-e5be-1dd2-7c19-d4c6a82d36ec@linaro.org>
Hi Richard,
On 9/24/21 23:53, Richard Henderson wrote:
> On 9/24/21 11:08 AM, WANG Xuerui wrote:
>> Oops, for some reason I only received this at about 8 pm...
>
> That was my fault. I wrote a bunch of stuff off-line yesterday while
> traveling, and the mail queue only flushed this morning.
>
> I'll note there's a bug in my example code wrt initializing rd with
> addi, then overwriting with cu32i.d.
>
> I like your v4 version of movi, with the high-bit-set predicate. The
> only case I can think of that you miss is e.g. 0x7fffffffffffffff,
> which can be
>
> addi.w rd, zero, -1
> cu52i.d rd, rd, 0x7ff
>
> One possibility is to extract a subroutine:
>
> static void tcg_out_movi_i32(TCGContext *s, TCGReg rd, int32_t val)
> {
> /* Single instruction cases */
> /* else lu12i.w + ori */
> }
>
> static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
> tcg_target_long val)
> {
> if (type == TCG_TYPE_I32 || val == (int32_t)val) {
> tcg_out_movi_i32(s, rd, val);
> return;
> }
>
> /* PC-relative cases */
>
> if (ctz64(val) >= 52) {
> tcg_out_opc_cu52i_d(s, rd, TCG_REG_ZERO, val >> 52);
> return;
> }
>
> /* Slow path. Initialize the low 32-bits, then concat high bits. */
> tcg_out_movi_i32(s, rd, val);
>
> rd_high_bits_are_ones = (int32_t)val < 0);
>
> /* Your imm_part_needs_loading checks; rd is always written. */
> }
>
This is so impressive understanding of the LoongArch assembly, working
around cu32i.d's single operand limitation so nicely. I'll just
(shamelessly) take this for v5, thanks again!
>
> r~
next prev parent reply other threads:[~2021-09-24 16:28 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-22 18:08 [PATCH v3 00/30] LoongArch64 port of QEMU TCG WANG Xuerui
2021-09-22 18:08 ` [PATCH v3 01/30] elf: Add machine type value for LoongArch WANG Xuerui
2021-09-22 18:17 ` Richard Henderson
2021-09-22 18:23 ` Philippe Mathieu-Daudé
2021-09-22 18:08 ` [PATCH v3 02/30] MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainer WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 03/30] tcg/loongarch64: Add the tcg-target.h file WANG Xuerui
2021-09-22 18:34 ` Philippe Mathieu-Daudé
2021-09-22 18:47 ` WANG Xuerui
2021-09-22 18:58 ` Richard Henderson
2021-09-23 10:35 ` Philippe Mathieu-Daudé
2021-09-22 18:09 ` [PATCH v3 04/30] tcg/loongarch64: Add generated instruction opcodes and encoding helpers WANG Xuerui
2021-09-22 18:37 ` Philippe Mathieu-Daudé
2021-09-22 18:51 ` WANG Xuerui
2021-09-22 19:32 ` Philippe Mathieu-Daudé
2021-09-22 18:09 ` [PATCH v3 05/30] tcg/loongarch64: Add register names, allocation order and input/output sets WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 06/30] tcg/loongarch64: Define the operand constraints WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 07/30] tcg/loongarch64: Implement necessary relocation operations WANG Xuerui
2021-09-22 18:41 ` Philippe Mathieu-Daudé
2021-09-22 18:55 ` WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 08/30] tcg/loongarch64: Implement the memory barrier op WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi WANG Xuerui
2021-09-22 18:39 ` Richard Henderson
2021-09-22 19:02 ` WANG Xuerui
2021-09-22 18:51 ` Richard Henderson
2021-09-23 15:38 ` WANG Xuerui
2021-09-23 16:50 ` Richard Henderson
2021-09-24 15:08 ` WANG Xuerui
2021-09-24 15:53 ` Richard Henderson
2021-09-24 16:26 ` WANG Xuerui [this message]
2021-09-22 18:09 ` [PATCH v3 10/30] tcg/loongarch64: Implement goto_ptr WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 11/30] tcg/loongarch64: Implement sign-/zero-extension ops WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 12/30] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 13/30] tcg/loongarch64: Implement deposit/extract ops WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 14/30] tcg/loongarch64: Implement bswap{16,32,64} ops WANG Xuerui
2021-09-22 18:23 ` Richard Henderson
2021-09-22 18:09 ` [PATCH v3 15/30] tcg/loongarch64: Implement clz/ctz ops WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 16/30] tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 17/30] tcg/loongarch64: Implement add/sub ops WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 18/30] tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 19/30] tcg/loongarch64: Implement br/brcond ops WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 20/30] tcg/loongarch64: Implement setcond ops WANG Xuerui
2021-09-22 18:25 ` Richard Henderson
2021-09-22 18:09 ` [PATCH v3 21/30] tcg/loongarch64: Implement tcg_out_call WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 22/30] tcg/loongarch64: Implement simple load/store ops WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 23/30] tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops WANG Xuerui
2021-09-23 17:25 ` Richard Henderson
2021-09-22 18:09 ` [PATCH v3 24/30] tcg/loongarch64: Implement tcg_target_qemu_prologue WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 25/30] tcg/loongarch64: Implement exit_tb/goto_tb WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 26/30] tcg/loongarch64: Implement tcg_target_init WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 27/30] tcg/loongarch64: Register the JIT WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 28/30] linux-user: Add safe syscall handling for loongarch64 hosts WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 29/30] accel/tcg/user-exec: Implement CPU-specific signal handler " WANG Xuerui
2021-09-22 18:09 ` [PATCH v3 30/30] configure, meson.build: Mark support " WANG Xuerui
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