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From: Laurent Vivier <laurent@vivier.eu>
To: David Gibson <david@gibson.dropbear.id.au>
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
	"QEMU Developers" <qemu-devel@nongnu.org>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Aurelien Jarno" <aurelien@aurel32.net>,
	"Richard Henderson" <richard.henderson@linaro.org>
Subject: Re: [Qemu-devel] [PATCH] softfloat: don't execute ppc64 ISA 3.0B instruction if it is not supported
Date: Sun, 4 Nov 2018 11:30:15 +0100	[thread overview]
Message-ID: <218eb47d-01a2-5247-d6af-329dab76b8c3@vivier.eu> (raw)
In-Reply-To: <20181103125713.GB24365@umbus.hotspot.internet-for-guests.com>

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On 03/11/2018 13:57, David Gibson wrote:
> On Thu, Nov 01, 2018 at 06:54:59PM +0100, Laurent Vivier wrote:
>> On 01/11/2018 18:49, Peter Maydell wrote:
>>> On 1 November 2018 at 17:38, Laurent Vivier <laurent@vivier.eu> wrote:
>>>> commit 27ae5109a2 has introduced an assembly instruction only supported
>>>> by ISA 3.0B and it fails to execute on previous versions of the POWER
>>>> CPU (like PowerPC G5).
>>>>
>>>> This patch fixes that by checking the ISA level, and falls back to
>>>> the default C function if the instruction is not supported.
>>>>
>>>> Fixes: 27ae5109a2ba8b6b679cce3e03e16570a34390a0
>>>>        (softfloat: Specialize udiv_qrnnd for ppc64)
>>>> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
>>>> ---
>>>>  include/fpu/softfloat-macros.h | 39 ++++++++++++++++++++--------------
>>>>  1 file changed, 23 insertions(+), 16 deletions(-)
>>>>
>>>> diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h
>>>> index c86687fa5e..fe98b33df9 100644
>>>> --- a/include/fpu/softfloat-macros.h
>>>> +++ b/include/fpu/softfloat-macros.h
>>>> @@ -78,6 +78,9 @@ this code that are retained.
>>>>  /* Portions of this work are licensed under the terms of the GNU GPL,
>>>>   * version 2 or later. See the COPYING file in the top-level directory.
>>>>   */
>>>> +#if defined(_ARCH_PPC64)
>>>> +extern bool have_isa_3_00;
>>>> +#endif
>>>
>>> I was wondering where this bool came from. The answer is
>>> that it's defined in tcg/ppc/tcg-target.inc.c. It's ok to
>>> use it here because fpu/softfloat.c is only compiled if
>>> CONFIG_TCG is true, so the tcg code will be present. The
>>> other user of this include file is target/m68k/softfloat.c,
>>> which also will only be compiled for a ppc host if CONFIG_TCG.
>>>
>>> It's a little awkward to be borrowing this tcg/ppc internal
>>> flag into the softfloat code, though.
>>
>> I agree, I was hopping Richard can advice another way to do that.
> 
> We already have ISA version flags in insns_flags & insns_flags2, so
> I'm hoping we can use those rather than introduce a new bool.
> 

Richard has sent another patch using "defined(_ARCH_PWR7)"

Thanks,
Laurent


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  reply	other threads:[~2018-11-04 10:30 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-01 17:38 [Qemu-devel] [PATCH] softfloat: don't execute ppc64 ISA 3.0B instruction if it is not supported Laurent Vivier
2018-11-01 17:49 ` Peter Maydell
2018-11-01 17:54   ` Laurent Vivier
2018-11-03 12:57     ` David Gibson
2018-11-04 10:30       ` Laurent Vivier [this message]
2018-11-01 19:52 ` Richard Henderson

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