From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm <qemu-arm@nongnu.org>,
QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH] target/arm: Fix SMLAD incorrect setting of Q bit
Date: Fri, 9 Oct 2020 17:36:33 -0500 [thread overview]
Message-ID: <21d142c5-d651-269a-8fbb-d35a743f1945@linaro.org> (raw)
In-Reply-To: <CAFEAcA8BiQcJJr3hkzTqnFLpYtXf1xbDf+GpgvYnPjJr_FAEUA@mail.gmail.com>
On 10/9/20 1:48 PM, Peter Maydell wrote:
> On Fri, 9 Oct 2020 at 15:47, Peter Maydell <peter.maydell@linaro.org> wrote:
>> + tcg_gen_extr_i64_i32(t1, t2, p64);
>
> Oh, I forgot to mention, but it looks like extr_i64_i32
> isn't documented in tcg/README. Is that because it isn't
> really a TCG IR op, or just an omission?
Because it's not an IR op. It's the combo of extrl and extrh.
r~
next prev parent reply other threads:[~2020-10-09 22:37 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-09 14:47 [PATCH] target/arm: Fix SMLAD incorrect setting of Q bit Peter Maydell
2020-10-09 17:57 ` Richard Henderson
2020-10-09 18:47 ` Peter Maydell
2020-10-09 22:34 ` Richard Henderson
2020-10-09 18:48 ` Peter Maydell
2020-10-09 22:36 ` Richard Henderson [this message]
2020-10-10 12:48 ` Peter Maydell
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