* [Qemu-devel] [PATCH v4 01/55] target/mips: Add preprocessor constants for nanoMIPS
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 02/55] target/mips: Add nanoMIPS base instruction set opcodes Aleksandar Markovic
` (53 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Add ISA_NANOMIPS32 and CPU_NANOMIPS32 preprocessor constants.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/mips-defs.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index d239069..c8e9979 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -39,6 +39,7 @@
#define ISA_MIPS64R5 0x00001000
#define ISA_MIPS32R6 0x00002000
#define ISA_MIPS64R6 0x00004000
+#define ISA_NANOMIPS32 0x00008000
/* MIPS ASEs. */
#define ASE_MIPS16 0x00010000
@@ -87,6 +88,9 @@
#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
+/* Wave Computing: "nanoMIPS" */
+#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
+
/* Strictly follow the architecture standard:
- Disallow "special" instruction handling for PMON/SPIM.
Note that we still maintain Count/Compare to match the host clock. */
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 02/55] target/mips: Add nanoMIPS base instruction set opcodes
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 01/55] target/mips: Add preprocessor constants for nanoMIPS Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 03/55] target/mips: Add nanoMIPS DSP ASE opcodes Aleksandar Markovic
` (52 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Yongbok Kim <yongbok.kim@mips.com>
Add nanoMIPS opcodes. nanoMIPS instruction are organized by so-called
instruction pools. Each pool contains a set of opcodes, that in turn
can be instruction opcodes or instruction pool opcodes.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/translate.c | 670 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 670 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index de0d55b..6a99a61 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -15644,6 +15644,676 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx)
return 2;
}
+/*
+ *
+ * nanoMIPS opcodes
+ *
+ */
+
+/* MAJOR, P16, and P32 pools opcodes */
+enum {
+ NM_P_ADDIU = 0x00,
+ NM_ADDIUPC = 0x01,
+ NM_MOVE_BALC = 0x02,
+ NM_P16_MV = 0x04,
+ NM_LW16 = 0x05,
+ NM_BC16 = 0x06,
+ NM_P16_SR = 0x07,
+
+ NM_POOL32A = 0x08,
+ NM_P_BAL = 0x0a,
+ NM_P16_SHIFT = 0x0c,
+ NM_LWSP16 = 0x0d,
+ NM_BALC16 = 0x0e,
+ NM_P16_4X4 = 0x0f,
+
+ NM_P_GP_W = 0x10,
+ NM_P_GP_BH = 0x11,
+ NM_P_J = 0x12,
+ NM_P16C = 0x14,
+ NM_LWGP16 = 0x15,
+ NM_P16_LB = 0x17,
+
+ NM_P48I = 0x18,
+ NM_P16_A1 = 0x1c,
+ NM_LW4X4 = 0x1d,
+ NM_P16_LH = 0x1f,
+
+ NM_P_U12 = 0x20,
+ NM_P_LS_U12 = 0x21,
+ NM_P_BR1 = 0x22,
+ NM_P16_A2 = 0x24,
+ NM_SW16 = 0x25,
+ NM_BEQZC16 = 0x26,
+
+ NM_POOL32F = 0x28,
+ NM_P_LS_S9 = 0x29,
+ NM_P_BR2 = 0x2a,
+
+ NM_P16_ADDU = 0x2c,
+ NM_SWSP16 = 0x2d,
+ NM_BNEZC16 = 0x2e,
+ NM_MOVEP = 0x2f,
+
+ NM_POOL32S = 0x30,
+ NM_P_BRI = 0x32,
+ NM_LI16 = 0x34,
+ NM_SWGP16 = 0x35,
+ NM_P16_BR = 0x36,
+
+ NM_P_LUI = 0x38,
+ NM_ANDI16 = 0x3c,
+ NM_SW4X4 = 0x3d,
+ NM_MOVEPREV = 0x3f,
+};
+
+/* POOL32A instruction pool */
+enum {
+ NM_POOL32A0 = 0x00,
+ NM_SPECIAL2 = 0x01,
+ NM_COP2_1 = 0x02,
+ NM_UDI = 0x03,
+ NM_POOL32A5 = 0x05,
+ NM_POOL32A7 = 0x07,
+};
+
+/* P.GP.W instruction pool */
+enum {
+ NM_ADDIUGP_W = 0x00,
+ NM_LWGP = 0x02,
+ NM_SWGP = 0x03,
+};
+
+/* P48I instruction pool */
+enum {
+ NM_LI48 = 0x00,
+ NM_ADDIU48 = 0x01,
+ NM_ADDIUGP48 = 0x02,
+ NM_ADDIUPC48 = 0x03,
+ NM_LWPC48 = 0x0b,
+ NM_SWPC48 = 0x0f,
+};
+
+/* P.U12 instruction pool */
+enum {
+ NM_ORI = 0x00,
+ NM_XORI = 0x01,
+ NM_ANDI = 0x02,
+ NM_P_SR = 0x03,
+ NM_SLTI = 0x04,
+ NM_SLTIU = 0x05,
+ NM_SEQI = 0x06,
+ NM_ADDIUNEG = 0x08,
+ NM_P_SHIFT = 0x0c,
+ NM_P_ROTX = 0x0d,
+ NM_P_INS = 0x0e,
+ NM_P_EXT = 0x0f,
+};
+
+/* POOL32F instruction pool */
+enum {
+ NM_POOL32F_0 = 0x00,
+ NM_POOL32F_3 = 0x03,
+ NM_POOL32F_5 = 0x05,
+};
+
+/* POOL32S instruction pool */
+enum {
+ NM_POOL32S_0 = 0x00,
+ NM_POOL32S_4 = 0x04,
+};
+
+/* P.LUI instruction pool */
+enum {
+ NM_LUI = 0x00,
+ NM_ALUIPC = 0x01,
+};
+
+/* P.GP.BH instruction pool */
+enum {
+ NM_LBGP = 0x00,
+ NM_SBGP = 0x01,
+ NM_LBUGP = 0x02,
+ NM_ADDIUGP_B = 0x03,
+ NM_P_GP_LH = 0x04,
+ NM_P_GP_SH = 0x05,
+ NM_P_GP_CP1 = 0x06,
+};
+
+/* P.LS.U12 instruction pool */
+enum {
+ NM_LB = 0x00,
+ NM_SB = 0x01,
+ NM_LBU = 0x02,
+ NM_P_PREFU12 = 0x03,
+ NM_LH = 0x04,
+ NM_SH = 0x05,
+ NM_LHU = 0x06,
+ NM_LWU = 0x07,
+ NM_LW = 0x08,
+ NM_SW = 0x09,
+ NM_LWC1 = 0x0a,
+ NM_SWC1 = 0x0b,
+ NM_LDC1 = 0x0e,
+ NM_SDC1 = 0x0f,
+};
+
+/* P.LS.S9 instruction pool */
+enum {
+ NM_P_LS_S0 = 0x00,
+ NM_P_LS_S1 = 0x01,
+ NM_P_LS_E0 = 0x02,
+ NM_P_LS_WM = 0x04,
+ NM_P_LS_UAWM = 0x05,
+};
+
+/* P.BAL instruction pool */
+enum {
+ NM_BC = 0x00,
+ NM_BALC = 0x01,
+};
+
+/* P.J instruction pool */
+enum {
+ NM_JALRC = 0x00,
+ NM_JALRC_HB = 0x01,
+ NM_P_BALRSC = 0x08,
+};
+
+/* P.BR1 instruction pool */
+enum {
+ NM_BEQC = 0x00,
+ NM_P_BR3A = 0x01,
+ NM_BGEC = 0x02,
+ NM_BGEUC = 0x03,
+};
+
+/* P.BR2 instruction pool */
+enum {
+ NM_BNEC = 0x00,
+ NM_BLTC = 0x02,
+ NM_BLTUC = 0x03,
+};
+
+/* P.BRI instruction pool */
+enum {
+ NM_BEQIC = 0x00,
+ NM_BBEQZC = 0x01,
+ NM_BGEIC = 0x02,
+ NM_BGEIUC = 0x03,
+ NM_BNEIC = 0x04,
+ NM_BBNEZC = 0x05,
+ NM_BLTIC = 0x06,
+ NM_BLTIUC = 0x07,
+};
+
+/* P16.SHIFT instruction pool */
+enum {
+ NM_SLL16 = 0x00,
+ NM_SRL16 = 0x01,
+};
+
+/* POOL16C instruction pool */
+enum {
+ NM_POOL16C_0 = 0x00,
+ NM_LWXS16 = 0x01,
+};
+
+/* P16.A1 instruction pool */
+enum {
+ NM_ADDIUR1SP = 0x01,
+};
+
+/* P16.A2 instruction pool */
+enum {
+ NM_ADDIUR2 = 0x00,
+ NM_P_ADDIURS5 = 0x01,
+};
+
+/* P16.ADDU instruction pool */
+enum {
+ NM_ADDU16 = 0x00,
+ NM_SUBU16 = 0x01,
+};
+
+/* P16.SR instruction pool */
+enum {
+ NM_SAVE16 = 0x00,
+ NM_RESTORE_JRC16 = 0x01,
+};
+
+/* P16.4X4 instruction pool */
+enum {
+ NM_ADDU4X4 = 0x00,
+ NM_MUL4X4 = 0x01,
+};
+
+/* P16.LB instruction pool */
+enum {
+ NM_LB16 = 0x00,
+ NM_SB16 = 0x01,
+ NM_LBU16 = 0x02,
+};
+
+/* P16.LH instruction pool */
+enum {
+ NM_LH16 = 0x00,
+ NM_SH16 = 0x01,
+ NM_LHU16 = 0x02,
+};
+
+/* P.RI instruction pool */
+enum {
+ NM_SIGRIE = 0x00,
+ NM_P_SYSCALL = 0x01,
+ NM_BREAK = 0x02,
+ NM_SDBBP = 0x03,
+};
+
+/* POOL32A0 instruction pool */
+enum {
+ NM_P_TRAP = 0x00,
+ NM_SEB = 0x01,
+ NM_SLLV = 0x02,
+ NM_MUL = 0x03,
+ NM_MFC0 = 0x06,
+ NM_MFHC0 = 0x07,
+ NM_SEH = 0x09,
+ NM_SRLV = 0x0a,
+ NM_MUH = 0x0b,
+ NM_MTC0 = 0x0e,
+ NM_MTHC0 = 0x0f,
+ NM_SRAV = 0x12,
+ NM_MULU = 0x13,
+ NM_ROTRV = 0x1a,
+ NM_MUHU = 0x1b,
+ NM_ADD = 0x22,
+ NM_DIV = 0x23,
+ NM_ADDU = 0x2a,
+ NM_MOD = 0x2b,
+ NM_SUB = 0x32,
+ NM_DIVU = 0x33,
+ NM_RDHWR = 0x38,
+ NM_SUBU = 0x3a,
+ NM_MODU = 0x3b,
+ NM_P_CMOVE = 0x42,
+ NM_FORK = 0x45,
+ NM_MFTR = 0x46,
+ NM_MFHTR = 0x47,
+ NM_AND = 0x4a,
+ NM_YIELD = 0x4d,
+ NM_MTTR = 0x4e,
+ NM_MTHTR = 0x4f,
+ NM_OR = 0x52,
+ NM_D_E_MT_VPE = 0x56,
+ NM_NOR = 0x5a,
+ NM_XOR = 0x62,
+ NM_SLT = 0x6a,
+ NM_P_SLTU = 0x72,
+ NM_SOV = 0x7a,
+};
+
+/* POOL32A7 instruction pool */
+enum {
+ NM_P_LSX = 0x00,
+ NM_LSA = 0x01,
+ NM_EXTW = 0x03,
+ NM_POOL32AXF = 0x07,
+};
+
+/* P.SR instruction pool */
+enum {
+ NM_PP_SR = 0x00,
+ NM_P_SR_F = 0x01,
+};
+
+/* P.SHIFT instruction pool */
+enum {
+ NM_P_SLL = 0x00,
+ NM_SRL = 0x02,
+ NM_SRA = 0x04,
+ NM_ROTR = 0x06,
+};
+
+/* P.ROTX instruction pool */
+enum {
+ NM_ROTX = 0x00,
+};
+
+/* P.INS instruction pool */
+enum {
+ NM_INS = 0x00,
+};
+
+/* P.EXT instruction pool */
+enum {
+ NM_EXT = 0x00,
+};
+
+/* POOL32F_0 (fmt) instruction pool */
+enum {
+ NM_RINT_S = 0x04,
+ NM_RINT_D = 0x44,
+ NM_ADD_S = 0x06,
+ NM_SELEQZ_S = 0x07,
+ NM_SELEQZ_D = 0x47,
+ NM_CLASS_S = 0x0c,
+ NM_CLASS_D = 0x4c,
+ NM_SUB_S = 0x0e,
+ NM_SELNEZ_S = 0x0f,
+ NM_SELNEZ_D = 0x4f,
+ NM_MUL_S = 0x16,
+ NM_SEL_S = 0x17,
+ NM_SEL_D = 0x57,
+ NM_DIV_S = 0x1e,
+ NM_ADD_D = 0x26,
+ NM_SUB_D = 0x2e,
+ NM_MUL_D = 0x36,
+ NM_MADDF_S = 0x37,
+ NM_MADDF_D = 0x77,
+ NM_DIV_D = 0x3e,
+ NM_MSUBF_S = 0x3f,
+ NM_MSUBF_D = 0x7f,
+};
+
+/* POOL32F_3 instruction pool */
+enum {
+ NM_MIN_FMT = 0x00,
+ NM_MAX_FMT = 0x01,
+ NM_MINA_FMT = 0x04,
+ NM_MAXA_FMT = 0x05,
+ NM_POOL32FXF = 0x07,
+};
+
+/* POOL32F_5 instruction pool */
+enum {
+ NM_CMP_CONDN_S = 0x00,
+ NM_CMP_CONDN_D = 0x02,
+};
+
+/* P.GP.LH instruction pool */
+enum {
+ NM_LHGP = 0x00,
+ NM_LHUGP = 0x01,
+};
+
+/* P.GP.SH instruction pool */
+enum {
+ NM_SHGP = 0x00,
+};
+
+/* P.GP.CP1 instruction pool */
+enum {
+ NM_LWC1GP = 0x00,
+ NM_SWC1GP = 0x01,
+ NM_LDC1GP = 0x02,
+ NM_SDC1GP = 0x03,
+};
+
+/* P.LS.S0 instruction pool */
+enum {
+ NM_LBS9 = 0x00,
+ NM_LHS9 = 0x04,
+ NM_LWS9 = 0x08,
+ NM_LDS9 = 0x0c,
+
+ NM_SBS9 = 0x01,
+ NM_SHS9 = 0x05,
+ NM_SWS9 = 0x09,
+ NM_SDS9 = 0x0d,
+
+ NM_LBUS9 = 0x02,
+ NM_LHUS9 = 0x06,
+ NM_LWC1S9 = 0x0a,
+ NM_LDC1S9 = 0x0e,
+
+ NM_P_PREFS9 = 0x03,
+ NM_LWUS9 = 0x07,
+ NM_SWC1S9 = 0x0b,
+ NM_SDC1S9 = 0x0f,
+};
+
+/* P.LS.S1 instruction pool */
+enum {
+ NM_ASET_ACLR = 0x02,
+ NM_UALH = 0x04,
+ NM_UASH = 0x05,
+ NM_CACHE = 0x07,
+ NM_P_LL = 0x0a,
+ NM_P_SC = 0x0b,
+};
+
+/* P.LS.WM instruction pool */
+enum {
+ NM_LWM = 0x00,
+ NM_SWM = 0x01,
+};
+
+/* P.LS.UAWM instruction pool */
+enum {
+ NM_UALWM = 0x00,
+ NM_UASWM = 0x01,
+};
+
+/* P.BR3A instruction pool */
+enum {
+ NM_BC1EQZC = 0x00,
+ NM_BC1NEZC = 0x01,
+ NM_BC2EQZC = 0x02,
+ NM_BC2NEZC = 0x03,
+ NM_BPOSGE32C = 0x04,
+};
+
+/* P16.RI instruction pool */
+enum {
+ NM_P16_SYSCALL = 0x01,
+ NM_BREAK16 = 0x02,
+ NM_SDBBP16 = 0x03,
+};
+
+/* POOL16C_0 instruction pool */
+enum {
+ NM_POOL16C_00 = 0x00,
+};
+
+/* P16.JRC instruction pool */
+enum {
+ NM_JRC = 0x00,
+ NM_JALRC16 = 0x01,
+};
+
+/* P.SYSCALL instruction pool */
+enum {
+ NM_SYSCALL = 0x00,
+ NM_HYPCALL = 0x01,
+};
+
+/* P.TRAP instruction pool */
+enum {
+ NM_TEQ = 0x00,
+ NM_TNE = 0x01,
+};
+
+/* P.CMOVE instruction pool */
+enum {
+ NM_MOVZ = 0x00,
+ NM_MOVN = 0x01,
+};
+
+/* POOL32Axf instruction pool */
+enum {
+ NM_POOL32AXF_4 = 0x04,
+ NM_POOL32AXF_5 = 0x05,
+};
+
+/* POOL32Axf_{4, 5} instruction pool */
+enum {
+ NM_CLO = 0x25,
+ NM_CLZ = 0x2d,
+
+ NM_TLBP = 0x01,
+ NM_TLBR = 0x09,
+ NM_TLBWI = 0x11,
+ NM_TLBWR = 0x19,
+ NM_TLBINV = 0x03,
+ NM_TLBINVF = 0x0b,
+ NM_DI = 0x23,
+ NM_EI = 0x2b,
+ NM_RDPGPR = 0x70,
+ NM_WRPGPR = 0x78,
+ NM_WAIT = 0x61,
+ NM_DERET = 0x71,
+ NM_ERETX = 0x79,
+};
+
+/* PP.SR instruction pool */
+enum {
+ NM_SAVE = 0x00,
+ NM_RESTORE = 0x02,
+ NM_RESTORE_JRC = 0x03,
+};
+
+/* P.SR.F instruction pool */
+enum {
+ NM_SAVEF = 0x00,
+ NM_RESTOREF = 0x01,
+};
+
+/* P16.SYSCALL instruction pool */
+enum {
+ NM_SYSCALL16 = 0x00,
+ NM_HYPCALL16 = 0x01,
+};
+
+/* POOL16C_00 instruction pool */
+enum {
+ NM_NOT16 = 0x00,
+ NM_XOR16 = 0x01,
+ NM_AND16 = 0x02,
+ NM_OR16 = 0x03,
+};
+
+/* PP.LSX and PP.LSXS instruction pool */
+enum {
+ NM_LBX = 0x00,
+ NM_LHX = 0x04,
+ NM_LWX = 0x08,
+ NM_LDX = 0x0c,
+
+ NM_SBX = 0x01,
+ NM_SHX = 0x05,
+ NM_SWX = 0x09,
+ NM_SDX = 0x0d,
+
+ NM_LBUX = 0x02,
+ NM_LHUX = 0x06,
+ NM_LWC1X = 0x0a,
+ NM_LDC1X = 0x0e,
+
+ NM_LWUX = 0x07,
+ NM_SWC1X = 0x0b,
+ NM_SDC1X = 0x0f,
+
+ NM_LHXS = 0x04,
+ NM_LWXS = 0x08,
+ NM_LDXS = 0x0c,
+
+ NM_SHXS = 0x05,
+ NM_SWXS = 0x09,
+ NM_SDXS = 0x0d,
+
+ NM_LHUXS = 0x06,
+ NM_LWC1XS = 0x0a,
+ NM_LDC1XS = 0x0e,
+
+ NM_LWUXS = 0x07,
+ NM_SWC1XS = 0x0b,
+ NM_SDC1XS = 0x0f,
+};
+
+/* ERETx instruction pool */
+enum {
+ NM_ERET = 0x00,
+ NM_ERETNC = 0x01,
+};
+
+/* POOL32FxF_{0, 1} insturction pool */
+enum {
+ NM_CFC1 = 0x40,
+ NM_CTC1 = 0x60,
+ NM_MFC1 = 0x80,
+ NM_MTC1 = 0xa0,
+ NM_MFHC1 = 0xc0,
+ NM_MTHC1 = 0xe0,
+
+ NM_CVT_S_PL = 0x84,
+ NM_CVT_S_PU = 0xa4,
+
+ NM_CVT_L_S = 0x004,
+ NM_CVT_L_D = 0x104,
+ NM_CVT_W_S = 0x024,
+ NM_CVT_W_D = 0x124,
+
+ NM_RSQRT_S = 0x008,
+ NM_RSQRT_D = 0x108,
+
+ NM_SQRT_S = 0x028,
+ NM_SQRT_D = 0x128,
+
+ NM_RECIP_S = 0x048,
+ NM_RECIP_D = 0x148,
+
+ NM_FLOOR_L_S = 0x00c,
+ NM_FLOOR_L_D = 0x10c,
+
+ NM_FLOOR_W_S = 0x02c,
+ NM_FLOOR_W_D = 0x12c,
+
+ NM_CEIL_L_S = 0x04c,
+ NM_CEIL_L_D = 0x14c,
+ NM_CEIL_W_S = 0x06c,
+ NM_CEIL_W_D = 0x16c,
+ NM_TRUNC_L_S = 0x08c,
+ NM_TRUNC_L_D = 0x18c,
+ NM_TRUNC_W_S = 0x0ac,
+ NM_TRUNC_W_D = 0x1ac,
+ NM_ROUND_L_S = 0x0cc,
+ NM_ROUND_L_D = 0x1cc,
+ NM_ROUND_W_S = 0x0ec,
+ NM_ROUND_W_D = 0x1ec,
+
+ NM_MOV_S = 0x01,
+ NM_MOV_D = 0x81,
+ NM_ABS_S = 0x0d,
+ NM_ABS_D = 0x8d,
+ NM_NEG_S = 0x2d,
+ NM_NEG_D = 0xad,
+ NM_CVT_D_S = 0x04d,
+ NM_CVT_D_W = 0x0cd,
+ NM_CVT_D_L = 0x14d,
+ NM_CVT_S_D = 0x06d,
+ NM_CVT_S_W = 0x0ed,
+ NM_CVT_S_L = 0x16d,
+};
+
+/* P.LL instruction pool */
+enum {
+ NM_LL = 0x00,
+ NM_LLWP = 0x01,
+};
+
+/* P.SC instruction pool */
+enum {
+ NM_SC = 0x00,
+ NM_SCWP = 0x01,
+};
+
+/* P.DVP instruction pool */
+enum {
+ NM_DVP = 0x00,
+ NM_EVP = 0x01,
+};
+
/* SmartMIPS extension to MIPS32 */
#if defined(TARGET_MIPS64)
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 03/55] target/mips: Add nanoMIPS DSP ASE opcodes
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 01/55] target/mips: Add preprocessor constants for nanoMIPS Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 02/55] target/mips: Add nanoMIPS base instruction set opcodes Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 04/55] target/mips: Add placeholder and invocation of decode_nanomips_opc() Aleksandar Markovic
` (51 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Stefan Markovic <smarkovic@wavecomp.com>
Add nanoMIPS opcodes for DSP ASE instruction pools and instructions.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/translate.c | 144 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 144 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 6a99a61..227b2c0 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16142,10 +16142,154 @@ enum {
/* POOL32Axf instruction pool */
enum {
+ NM_POOL32AXF_1 = 0x01,
+ NM_POOL32AXF_2 = 0x02,
NM_POOL32AXF_4 = 0x04,
NM_POOL32AXF_5 = 0x05,
+ NM_POOL32AXF_7 = 0x07,
};
+/* POOL32Axf_1 instruction pool */
+enum {
+ NM_POOL32AXF_1_0 = 0x00,
+ NM_POOL32AXF_1_1 = 0x01,
+ NM_POOL32AXF_1_3 = 0x03,
+ NM_POOL32AXF_1_4 = 0x04,
+ NM_POOL32AXF_1_5 = 0x05,
+ NM_POOL32AXF_1_7 = 0x07,
+};
+
+/* POOL32Axf_2 instruction pool */
+enum {
+ NM_POOL32AXF_2_0_7 = 0x00,
+ NM_POOL32AXF_2_8_15 = 0x01,
+ NM_POOL32AXF_2_16_23 = 0x02,
+ NM_POOL32AXF_2_24_31 = 0x03,
+};
+
+/* POOL32Axf_{4, 5} instruction pool */
+enum {
+ /* nanoMIPS DSP instructions */
+ NM_ABSQ_S_QB = 0x00,
+ NM_ABSQ_S_PH = 0x08,
+ NM_ABSQ_S_W = 0x10,
+ NM_PRECEQ_W_PHL = 0x28,
+ NM_PRECEQ_W_PHR = 0x30,
+ NM_PRECEQU_PH_QBL = 0x38,
+ NM_PRECEQU_PH_QBR = 0x48,
+ NM_PRECEU_PH_QBL = 0x58,
+ NM_PRECEU_PH_QBR = 0x68,
+ NM_PRECEQU_PH_QBLA = 0x39,
+ NM_PRECEQU_PH_QBRA = 0x49,
+ NM_PRECEU_PH_QBLA = 0x59,
+ NM_PRECEU_PH_QBRA = 0x69,
+ NM_REPLV_PH = 0x01,
+ NM_REPLV_QB = 0x09,
+ NM_BITREV = 0x18,
+ NM_INSV = 0x20,
+ NM_RADDU_W_QB = 0x78,
+
+ NM_BITSWAP = 0x05,
+ NM_WSBH = 0x3d,
+};
+
+/* POOL32Axf_7 instruction pool */
+enum {
+ NM_SHRA_R_QB = 0x0,
+ NM_SHRL_PH = 0x1,
+ NM_REPL_QB = 0x2,
+};
+
+/* POOL32Axf_1_0 instruction pool */
+enum {
+ NM_MFHI = 0x0,
+ NM_MFLO = 0x1,
+ NM_MTHI = 0x2,
+ NM_MTLO = 0x3,
+};
+
+/* POOL32Axf_1_1 instruction pool */
+enum {
+ NM_MTHLIP = 0x0,
+ NM_SHILOV = 0x1,
+};
+
+/* POOL32Axf_1_3 instruction pool */
+enum {
+ NM_RDDSP = 0x0,
+ NM_WRDSP = 0x1,
+ NM_EXTP = 0x2,
+ NM_EXTPDP = 0x3,
+};
+
+/* POOL32Axf_1_4 instruction pool */
+enum {
+ NM_SHLL_QB = 0x0,
+ NM_SHRL_QB = 0x1,
+};
+
+/* POOL32Axf_1_5 instruction pool */
+enum {
+ NM_MAQ_S_W_PHR = 0x0,
+ NM_MAQ_S_W_PHL = 0x1,
+ NM_MAQ_SA_W_PHR = 0x2,
+ NM_MAQ_SA_W_PHL = 0x3,
+};
+
+/* POOL32Axf_1_7 instruction pool */
+enum {
+ NM_EXTR_W = 0x0,
+ NM_EXTR_R_W = 0x1,
+ NM_EXTR_RS_W = 0x2,
+ NM_EXTR_S_H = 0x3,
+};
+
+/* POOL32Axf_2_0_7 instruction pool */
+enum {
+ NM_DPA_W_PH = 0x0,
+ NM_DPAQ_S_W_PH = 0x1,
+ NM_DPS_W_PH = 0x2,
+ NM_DPSQ_S_W_PH = 0x3,
+ NM_BALIGN = 0x4,
+ NM_MADD = 0x5,
+ NM_MULT = 0x6,
+ NM_EXTRV_W = 0x7,
+};
+
+/* POOL32Axf_2_8_15 instruction pool */
+enum {
+ NM_DPAX_W_PH = 0x0,
+ NM_DPAQ_SA_L_W = 0x1,
+ NM_DPSX_W_PH = 0x2,
+ NM_DPSQ_SA_L_W = 0x3,
+ NM_MADDU = 0x5,
+ NM_MULTU = 0x6,
+ NM_EXTRV_R_W = 0x7,
+};
+
+/* POOL32Axf_2_16_23 instruction pool */
+enum {
+ NM_DPAU_H_QBL = 0x0,
+ NM_DPAQX_S_W_PH = 0x1,
+ NM_DPSU_H_QBL = 0x2,
+ NM_DPSQX_S_W_PH = 0x3,
+ NM_EXTPV = 0x4,
+ NM_MSUB = 0x5,
+ NM_MULSA_W_PH = 0x6,
+ NM_EXTRV_RS_W = 0x7,
+};
+
+/* POOL32Axf_2_24_31 instruction pool */
+enum {
+ NM_DPAU_H_QBR = 0x0,
+ NM_DPAQX_SA_W_PH = 0x1,
+ NM_DPSU_H_QBR = 0x2,
+ NM_DPSQX_SA_W_PH = 0x3,
+ NM_EXTPDPV = 0x4,
+ NM_MSUBU = 0x5,
+ NM_MULSAQ_S_W_PH = 0x6,
+ NM_EXTRV_S_H = 0x7,
+};
/* POOL32Axf_{4, 5} instruction pool */
enum {
NM_CLO = 0x25,
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 04/55] target/mips: Add placeholder and invocation of decode_nanomips_opc()
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (2 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 03/55] target/mips: Add nanoMIPS DSP ASE opcodes Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 19:22 ` Richard Henderson
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 05/55] target/mips: Add nanoMIPS decoding and extraction utilities Aleksandar Markovic
` (50 subsequent siblings)
54 siblings, 1 reply; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Add empty body and invocation of decode_nanomips_opc() if the bit
ISA_NANOMIPS32 is set in ctx->insn_flags.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/translate.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 227b2c0..c64efbe 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16458,6 +16458,19 @@ enum {
NM_EVP = 0x01,
};
+
+/*
+ *
+ * nanoMIPS decoding engine
+ *
+ */
+
+static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
+{
+ return 2;
+}
+
+
/* SmartMIPS extension to MIPS32 */
#if defined(TARGET_MIPS64)
@@ -21262,6 +21275,9 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
insn_bytes = 4;
decode_opc(env, ctx);
+ } else if (ctx->insn_flags & ISA_NANOMIPS32) {
+ ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
+ insn_bytes = decode_nanomips_opc(env, ctx);
} else if (ctx->insn_flags & ASE_MICROMIPS) {
ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
insn_bytes = decode_micromips_opc(env, ctx);
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v4 04/55] target/mips: Add placeholder and invocation of decode_nanomips_opc()
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 04/55] target/mips: Add placeholder and invocation of decode_nanomips_opc() Aleksandar Markovic
@ 2018-07-24 19:22 ` Richard Henderson
0 siblings, 0 replies; 65+ messages in thread
From: Richard Henderson @ 2018-07-24 19:22 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien, amarkovic,
smarkovic, pjovanovic, pburton
On 07/24/2018 10:31 AM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> Add empty body and invocation of decode_nanomips_opc() if the bit
> ISA_NANOMIPS32 is set in ctx->insn_flags.
>
> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
> ---
> target/mips/translate.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v4 05/55] target/mips: Add nanoMIPS decoding and extraction utilities
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (3 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 04/55] target/mips: Add placeholder and invocation of decode_nanomips_opc() Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 19:22 ` Richard Henderson
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 06/55] target/mips: Add emulation of misc nanoMIPS 16-bit instructions Aleksandar Markovic
` (49 subsequent siblings)
54 siblings, 1 reply; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Add some basic utility functions and macros for nanoMIPS decoding
engine.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/translate.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c64efbe..2ddc6c9 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16465,6 +16465,51 @@ enum {
*
*/
+/* Implement nanoMIPS pseudocode decode_gpr(encoded_gpr, 'gpr3'). */
+static inline int decode_gpr_gpr3(int r)
+{
+ static const int map[] = { 16, 17, 18, 19, 4, 5, 6, 7 };
+
+ return map[r & 0x7];
+}
+
+/* Implement nanoMIPS pseudocode decode_gpr(encoded_gpr, 'gpr3.src.store'). */
+static inline int decode_gpr_gpr3_src_store(int r)
+{
+ static const int map[] = { 0, 17, 18, 19, 4, 5, 6, 7 };
+
+ return map[r & 0x7];
+}
+
+/* Implement nanoMIPS pseudocode decode_gpr(encoded_gpr, 'gpr4'). */
+static inline int decode_gpr_gpr4(int r)
+{
+ static const int map[] = { 8, 9, 10, 11, 4, 5, 6, 7,
+ 16, 17, 18, 19, 20, 21, 22, 23 };
+
+ return map[r & 0xf];
+}
+
+/* Implement nanoMIPS pseudocode decode_gpr(encoded_gpr, 'gpr4.zero'). */
+static inline int decode_gpr_gpr4_zero(int r)
+{
+ static const int map[] = { 8, 9, 10, 0, 4, 5, 6, 7,
+ 16, 17, 18, 19, 20, 21, 22, 23 };
+
+ return map[r & 0xf];
+}
+
+
+/* extraction utilities */
+
+#define NANOMIPS_EXTRACT_RD(op) ((op >> 7) & 0x7)
+#define NANOMIPS_EXTRACT_RS(op) ((op >> 4) & 0x7)
+#define NANOMIPS_EXTRACT_RS2(op) uMIPS_RS(op)
+#define NANOMIPS_EXTRACT_RS1(op) ((op >> 1) & 0x7)
+#define NANOMIPS_EXTRACT_RD5(op) ((op >> 5) & 0x1f)
+#define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f)
+
+
static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
{
return 2;
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v4 05/55] target/mips: Add nanoMIPS decoding and extraction utilities
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 05/55] target/mips: Add nanoMIPS decoding and extraction utilities Aleksandar Markovic
@ 2018-07-24 19:22 ` Richard Henderson
0 siblings, 0 replies; 65+ messages in thread
From: Richard Henderson @ 2018-07-24 19:22 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien, amarkovic,
smarkovic, pjovanovic, pburton
On 07/24/2018 10:31 AM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> Add some basic utility functions and macros for nanoMIPS decoding
> engine.
>
> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
> ---
> target/mips/translate.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v4 06/55] target/mips: Add emulation of misc nanoMIPS 16-bit instructions
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (4 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 05/55] target/mips: Add nanoMIPS decoding and extraction utilities Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 19:27 ` Richard Henderson
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 07/55] target/mips: Add emulation of nanoMIPS 16-bit load and store instructions Aleksandar Markovic
` (48 subsequent siblings)
54 siblings, 1 reply; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Yongbok Kim <yongbok.kim@mips.com>
Add emulation of misc nanoMIPS 16-bit instructions from instruction
pools P16, P16.BR, P16.BRI, P16.4X4 and other related pools.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/translate.c | 260 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 260 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 2ddc6c9..076637c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16512,6 +16512,266 @@ static inline int decode_gpr_gpr4_zero(int r)
static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
{
+ uint32_t op;
+ int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode));
+ int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
+ int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS1(ctx->opcode));
+
+ /* make sure instructions are on a halfword boundary */
+ if (ctx->base.pc_next & 0x1) {
+ TCGv tmp = tcg_const_tl(ctx->base.pc_next);
+ tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
+ tcg_temp_free(tmp);
+ return 2;
+ }
+
+ op = extract32(ctx->opcode, 10, 6);
+ switch (op) {
+ case NM_P16_MV:
+ {
+ int rt1 = NANOMIPS_EXTRACT_RD5(ctx->opcode);
+ if (rt1 != 0) {
+ /* MOVE */
+ int rs1 = NANOMIPS_EXTRACT_RS5(ctx->opcode);
+ gen_arith(ctx, OPC_ADDU, rt1, rs1, 0);
+ } else {
+ /* P16.RI */
+ switch (extract32(ctx->opcode, 3, 2)) {
+ case NM_P16_SYSCALL:
+ if (extract32(ctx->opcode, 2, 1) == 0) {
+ generate_exception_end(ctx, EXCP_SYSCALL);
+ } else {
+ generate_exception_end(ctx, EXCP_RI);
+ }
+ break;
+ case NM_BREAK16:
+ generate_exception_end(ctx, EXCP_BREAK);
+ break;
+ case NM_SDBBP16:
+ if (is_uhi(extract32(ctx->opcode, 0, 3))) {
+ gen_helper_do_semihosting(cpu_env);
+ } else {
+ if (ctx->hflags & MIPS_HFLAG_SBRI) {
+ generate_exception_end(ctx, EXCP_RI);
+ } else {
+ generate_exception_end(ctx, EXCP_DBp);
+ }
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ }
+ }
+ break;
+ case NM_P16_SHIFT:
+ {
+ int shift = extract32(ctx->opcode, 0, 3);
+ uint32_t opc = 0;
+ shift = (shift == 0) ? 8 : shift;
+
+ switch (extract32(ctx->opcode, 3, 1)) {
+ case NM_SLL16:
+ opc = OPC_SLL;
+ break;
+ case NM_SRL16:
+ opc = OPC_SRL;
+ break;
+ }
+ gen_shift_imm(ctx, opc, rt, rs, shift);
+ }
+ break;
+ case NM_P16C:
+ break;
+ case NM_P16_A1:
+ switch (extract32(ctx->opcode, 6, 1)) {
+ case NM_ADDIUR1SP:
+ gen_arith_imm(ctx, OPC_ADDIU, rt, 29,
+ extract32(ctx->opcode, 0, 6) << 2);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ case NM_P16_A2:
+ switch (extract32(ctx->opcode, 3, 1)) {
+ case NM_ADDIUR2:
+ {
+ uint8_t u = extract32(ctx->opcode, 0, 3) << 2;
+ gen_arith_imm(ctx, OPC_ADDIU, rt, rs, u);
+ }
+ break;
+ case NM_P_ADDIURS5:
+ {
+ int rt1 = extract32(ctx->opcode, 5, 5);
+ if (rt1 != 0) {
+ int s = (sextract32(ctx->opcode, 4, 1) << 3) |
+ extract32(ctx->opcode, 0, 3);
+ /* s = sign_extend( s[3] . s[2:0] , from_nbits = 4)*/
+ gen_arith_imm(ctx, OPC_ADDIU, rt1, rt1, s);
+ }
+ }
+ break;
+ }
+ break;
+ case NM_P16_ADDU:
+ switch (ctx->opcode & 0x1) {
+ case NM_ADDU16:
+ gen_arith(ctx, OPC_ADDU, rd, rs, rt);
+ break;
+ case NM_SUBU16:
+ gen_arith(ctx, OPC_SUBU, rd, rs, rt);
+ break;
+ }
+ break;
+ case NM_P16_4X4:
+ {
+ int rt1 = (extract32(ctx->opcode, 9, 1) << 3) |
+ extract32(ctx->opcode, 5, 3);
+ int rs1 = (extract32(ctx->opcode, 4, 1) << 3) |
+ extract32(ctx->opcode, 0, 3);
+ rt1 = decode_gpr_gpr4(rt1);
+ rs1 = decode_gpr_gpr4(rs1);
+
+ switch (((ctx->opcode >> 7) & 0x2) | ((ctx->opcode >> 3) & 0x1)) {
+ case NM_ADDU4X4:
+ gen_arith(ctx, OPC_ADDU, rt1, rs1, rt1);
+ break;
+ case NM_MUL4X4:
+ gen_r6_muldiv(ctx, R6_OPC_MUL, rt1, rs1, rt1);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ }
+ break;
+ case NM_LI16:
+ {
+ int imm = extract32(ctx->opcode, 0, 7);
+ imm = (imm == 0x7f ? -1 : imm);
+ if (rt != 0) {
+ tcg_gen_movi_tl(cpu_gpr[rt], imm);
+ }
+ }
+ break;
+ case NM_ANDI16:
+ {
+ uint32_t u = extract32(ctx->opcode, 0, 4);
+ u = (u == 12) ? 0xff :
+ (u == 13) ? 0xffff : u;
+ gen_logic_imm(ctx, OPC_ANDI, rt, rs, u);
+ }
+ break;
+ case NM_P16_LB:
+ break;
+ case NM_P16_LH:
+ break;
+ case NM_LW16:
+ break;
+ case NM_LWSP16:
+ break;
+ case NM_LW4X4:
+ break;
+ case NM_SW4X4:
+ break;
+ case NM_LWGP16:
+ break;
+ case NM_SWSP16:
+ break;
+ case NM_SW16:
+ break;
+ case NM_SWGP16:
+ break;
+ case NM_BC16:
+ gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0,
+ (sextract32(ctx->opcode, 0, 1) << 10) |
+ (extract32(ctx->opcode, 1, 9) << 1), 0);
+ break;
+ case NM_BALC16:
+ gen_compute_branch(ctx, OPC_BGEZAL, 2, 0, 0,
+ (sextract32(ctx->opcode, 0, 1) << 10) |
+ (extract32(ctx->opcode, 1, 9) << 1), 0);
+ break;
+ case NM_BEQZC16:
+ case NM_BNEZC16:
+ gen_compute_branch(ctx, op == NM_BNEZC16 ? OPC_BNE : OPC_BEQ, 2,
+ rt, 0,
+ (sextract32(ctx->opcode, 0, 1) << 7) |
+ (extract32(ctx->opcode, 1, 6) << 1), 0);
+ break;
+ case NM_P16_BR:
+ switch (ctx->opcode & 0xf) {
+ case 0:
+ /* P16.JRC */
+ switch (extract32(ctx->opcode, 4, 1)) {
+ case NM_JRC:
+ gen_compute_branch(ctx, OPC_JR, 2,
+ extract32(ctx->opcode, 5, 5), 0, 0, 0);
+ break;
+ case NM_JALRC16:
+ gen_compute_branch(ctx, OPC_JALR, 2,
+ extract32(ctx->opcode, 5, 5), 31, 0, 0);
+ break;
+ }
+ break;
+ default:
+ /* P16.BRI */
+ if (extract32(ctx->opcode, 4, 3) < extract32(ctx->opcode, 7, 3)) {
+ /* BEQC16 */
+ gen_compute_branch(ctx, OPC_BEQ, 2, rs, rt,
+ extract32(ctx->opcode, 0, 4) << 1, 0);
+ } else {
+ /* BNEC16 */
+ gen_compute_branch(ctx, OPC_BNE, 2, rs, rt,
+ extract32(ctx->opcode, 0, 4) << 1, 0);
+ }
+ break;
+ }
+ break;
+ case NM_P16_SR:
+ break;
+ case NM_MOVEP:
+ case NM_MOVEPREV:
+ {
+ static const int gpr2reg1[] = {4, 5, 6, 7};
+ static const int gpr2reg2[] = {5, 6, 7, 8};
+ int re;
+ int rd2 = extract32(ctx->opcode, 3, 1) << 1 |
+ extract32(ctx->opcode, 8, 1);
+ int r1 = gpr2reg1[rd2];
+ int r2 = gpr2reg2[rd2];
+ int r3 = extract32(ctx->opcode, 4, 1) << 3 |
+ extract32(ctx->opcode, 0, 3);
+ int r4 = extract32(ctx->opcode, 9, 1) << 3 |
+ extract32(ctx->opcode, 5, 3);
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ if (op == NM_MOVEP) {
+ rd = r1;
+ re = r2;
+ rs = decode_gpr_gpr4_zero(r3);
+ rt = decode_gpr_gpr4_zero(r4);
+ } else {
+ rd = decode_gpr_gpr4(r3);
+ re = decode_gpr_gpr4(r4);
+ rs = r1;
+ rt = r2;
+ }
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+ tcg_gen_mov_tl(cpu_gpr[rd], t0);
+ tcg_gen_mov_tl(cpu_gpr[re], t1);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+ break;
+ default:
+ break;
+ }
+
return 2;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v4 06/55] target/mips: Add emulation of misc nanoMIPS 16-bit instructions
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 06/55] target/mips: Add emulation of misc nanoMIPS 16-bit instructions Aleksandar Markovic
@ 2018-07-24 19:27 ` Richard Henderson
0 siblings, 0 replies; 65+ messages in thread
From: Richard Henderson @ 2018-07-24 19:27 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien, amarkovic,
smarkovic, pjovanovic, pburton
On 07/24/2018 10:31 AM, Aleksandar Markovic wrote:
> + /* make sure instructions are on a halfword boundary */
> + if (ctx->base.pc_next & 0x1) {
> + TCGv tmp = tcg_const_tl(ctx->base.pc_next);
> + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
> + tcg_temp_free(tmp);
> + return 2;
> + }
You've lost the actual raising of the exception since v3.
> + case NM_P16_MV:
> + {
> + int rt1 = NANOMIPS_EXTRACT_RD5(ctx->opcode);
> + if (rt1 != 0) {
> + /* MOVE */
> + int rs1 = NANOMIPS_EXTRACT_RS5(ctx->opcode);
> + gen_arith(ctx, OPC_ADDU, rt1, rs1, 0);
Why are you creating rt1 and rs1 variables?
I see you took my shadowed variables comment to heart, and renamed them, but
why not just overwrite the contents of the existing outer variable?
> + case NM_P_ADDIURS5:
> + {
> + int rt1 = extract32(ctx->opcode, 5, 5);
Likewise.
> + case NM_P16_4X4:
> + {
> + int rt1 = (extract32(ctx->opcode, 9, 1) << 3) |
> + extract32(ctx->opcode, 5, 3);
> + int rs1 = (extract32(ctx->opcode, 4, 1) << 3) |
> + extract32(ctx->opcode, 0, 3);
Likewise.
r~
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v4 07/55] target/mips: Add emulation of nanoMIPS 16-bit load and store instructions
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (5 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 06/55] target/mips: Add emulation of misc nanoMIPS 16-bit instructions Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 19:34 ` Richard Henderson
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 08/55] target/mips: Add emulation of nanoMIPS 16-bit logic instructions Aleksandar Markovic
` (47 subsequent siblings)
54 siblings, 1 reply; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Yongbok Kim <yongbok.kim@mips.com>
Add emulation of LWXS16, LB16, SB16, LBU16, LH16, SH16, LHU16, LW16, LWSP16,
LW4X4, SW4X4, LWGP16, SWSP16, SW16, and SWGP16 instructions.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/translate.c | 106 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 106 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 076637c..191bb15 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16583,6 +16583,13 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case NM_P16C:
+ switch (ctx->opcode & 1) {
+ case NM_POOL16C_0:
+ break;
+ case NM_LWXS16:
+ gen_ldxs(ctx, rt, rs, rd);
+ break;
+ }
break;
case NM_P16_A1:
switch (extract32(ctx->opcode, 6, 1)) {
@@ -16666,24 +16673,123 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case NM_P16_LB:
+ {
+ uint32_t u = extract32(ctx->opcode, 0, 2);
+ switch (((ctx->opcode) >> 2) & 0x03) {
+ case NM_LB16:
+ gen_ld(ctx, OPC_LB, rt, rs, u);
+ break;
+ case NM_SB16:
+ {
+ int rt = decode_gpr_gpr3_src_store(
+ NANOMIPS_EXTRACT_RD(ctx->opcode));
+ gen_st(ctx, OPC_SB, rt, rs, u);
+ }
+ break;
+ case NM_LBU16:
+ gen_ld(ctx, OPC_LBU, rt, rs, u);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ }
break;
case NM_P16_LH:
+ {
+ uint32_t u = extract32(ctx->opcode, 1, 2) << 1;
+ switch ((((ctx->opcode >> 3) & 1) << 1) | (ctx->opcode & 1)) {
+ case NM_LH16:
+ gen_ld(ctx, OPC_LH, rt, rs, u);
+ break;
+ case NM_SH16:
+ {
+ int rt = decode_gpr_gpr3_src_store(
+ NANOMIPS_EXTRACT_RD(ctx->opcode));
+ gen_st(ctx, OPC_SH, rt, rs, u);
+ }
+ break;
+ case NM_LHU16:
+ gen_ld(ctx, OPC_LHU, rt, rs, u);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ }
break;
case NM_LW16:
+ {
+ int u = extract32(ctx->opcode, 0, 4) << 2;
+ gen_ld(ctx, OPC_LW, rt, rs, u);
+ }
break;
case NM_LWSP16:
+ {
+ int rt = NANOMIPS_EXTRACT_RD5(ctx->opcode);
+ int u = extract32(ctx->opcode, 0, 5) << 2;
+
+ gen_ld(ctx, OPC_LW, rt, 29, u);
+ }
break;
case NM_LW4X4:
+ {
+ int rt = (extract32(ctx->opcode, 9, 1) << 3) |
+ extract32(ctx->opcode, 5, 3);
+ int rs = (extract32(ctx->opcode, 4, 1) << 3) |
+ extract32(ctx->opcode, 0, 3);
+ int u = (extract32(ctx->opcode, 3, 1) << 3) |
+ (extract32(ctx->opcode, 8, 1) << 2);
+ rt = decode_gpr_gpr4(rt);
+ rs = decode_gpr_gpr4(rs);
+ gen_ld(ctx, OPC_LW, rt, rs, u);
+ }
break;
case NM_SW4X4:
+ {
+ int rt = (extract32(ctx->opcode, 9, 1) << 3) |
+ extract32(ctx->opcode, 5, 3);
+ int rs = (extract32(ctx->opcode, 4, 1) << 3) |
+ extract32(ctx->opcode, 0, 3);
+ int u = (extract32(ctx->opcode, 3, 1) << 3) |
+ (extract32(ctx->opcode, 8, 1) << 2);
+ rt = decode_gpr_gpr4_zero(rt);
+ rs = decode_gpr_gpr4(rs);
+ gen_st(ctx, OPC_SW, rt, rs, u);
+ }
break;
case NM_LWGP16:
+ {
+ int u = extract32(ctx->opcode, 0, 7) << 2;
+ gen_ld(ctx, OPC_LW, rt, 28, u);
+ }
break;
case NM_SWSP16:
+ {
+ int rt = NANOMIPS_EXTRACT_RD5(ctx->opcode);
+ int u = extract32(ctx->opcode, 0, 5) << 2;
+
+ gen_st(ctx, OPC_SW, rt, 29, u);
+ }
break;
case NM_SW16:
+ {
+ int rt = decode_gpr_gpr3_src_store(
+ NANOMIPS_EXTRACT_RD(ctx->opcode));
+ int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
+ int u = extract32(ctx->opcode, 0, 4) << 2;
+
+ gen_st(ctx, OPC_SW, rt, rs, u);
+ }
break;
case NM_SWGP16:
+ {
+ int rt = decode_gpr_gpr3_src_store(
+ NANOMIPS_EXTRACT_RD(ctx->opcode));
+ int u = extract32(ctx->opcode, 0, 7) << 2;
+
+ gen_st(ctx, OPC_SW, rt, 28, u);
+ }
break;
case NM_BC16:
gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0,
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v4 07/55] target/mips: Add emulation of nanoMIPS 16-bit load and store instructions
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 07/55] target/mips: Add emulation of nanoMIPS 16-bit load and store instructions Aleksandar Markovic
@ 2018-07-24 19:34 ` Richard Henderson
2018-07-25 17:15 ` Aleksandar Markovic
0 siblings, 1 reply; 65+ messages in thread
From: Richard Henderson @ 2018-07-24 19:34 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien, amarkovic,
smarkovic, pjovanovic, pburton
On 07/24/2018 10:31 AM, Aleksandar Markovic wrote:
> + case NM_SB16:
> + {
> + int rt = decode_gpr_gpr3_src_store(
> + NANOMIPS_EXTRACT_RD(ctx->opcode));
Shadowed variable.
> + case NM_SH16:
> + {
> + int rt = decode_gpr_gpr3_src_store(
> + NANOMIPS_EXTRACT_RD(ctx->opcode));
Likewise.
> case NM_LWSP16:
> + {
> + int rt = NANOMIPS_EXTRACT_RD5(ctx->opcode);
Likewise.
> case NM_LW4X4:
> + {
> + int rt = (extract32(ctx->opcode, 9, 1) << 3) |
> + extract32(ctx->opcode, 5, 3);
> + int rs = (extract32(ctx->opcode, 4, 1) << 3) |
> + extract32(ctx->opcode, 0, 3);
Likewise.
> case NM_SW4X4:
> + {
> + int rt = (extract32(ctx->opcode, 9, 1) << 3) |
> + extract32(ctx->opcode, 5, 3);
> + int rs = (extract32(ctx->opcode, 4, 1) << 3) |
> + extract32(ctx->opcode, 0, 3);
Likewise.
> case NM_SWSP16:
> + {
> + int rt = NANOMIPS_EXTRACT_RD5(ctx->opcode);
Likewise.
> case NM_SW16:
> + {
> + int rt = decode_gpr_gpr3_src_store(
> + NANOMIPS_EXTRACT_RD(ctx->opcode));
> + int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
Likewise.
> case NM_SWGP16:
> + {
> + int rt = decode_gpr_gpr3_src_store(
> + NANOMIPS_EXTRACT_RD(ctx->opcode));
Likewise.
It might be handy to temporarily add
target/mips/translate.o: QEMU_CFLAGS += -Wshadow=local
to target/mips/Makefile.objs, but I don't know how prevalent that situation is
within the existing code base...
r~
^ permalink raw reply [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v4 07/55] target/mips: Add emulation of nanoMIPS 16-bit load and store instructions
2018-07-24 19:34 ` Richard Henderson
@ 2018-07-25 17:15 ` Aleksandar Markovic
0 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-25 17:15 UTC (permalink / raw)
To: Richard Henderson, Aleksandar Markovic, qemu-devel@nongnu.org
Cc: laurent@vivier.eu, riku.voipio@iki.fi,
philippe.mathieu.daude@gmail.com, aurelien@aurel32.net,
Stefan Markovic, Petar Jovanovic, Paul Burton
> It might be handy to temporarily add
>
> target/mips/translate.o: QEMU_CFLAGS += -Wshadow=local
>
> to target/mips/Makefile.objs, but I don't know how prevalent that situation is
> within the existing code base...
Richard, thanks for this useful tip. I did similar checks utilizing gcc warnings, but some other hard way. I see this can be handy for other situations too - for example, if using -Wimplicit-fallthrough...
Aleksandar M.
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v4 08/55] target/mips: Add emulation of nanoMIPS 16-bit logic instructions
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (6 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 07/55] target/mips: Add emulation of nanoMIPS 16-bit load and store instructions Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 09/55] target/mips: Add emulation of nanoMIPS 16-bit save and restore instructions Aleksandar Markovic
` (46 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Yongbok Kim <yongbok.kim@mips.com>
Add emulation of NOT16, AND16, XOR16, OR16 instructions.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/translate.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 191bb15..4ef7df8 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16510,6 +16510,27 @@ static inline int decode_gpr_gpr4_zero(int r)
#define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f)
+static void gen_pool16c_nanomips_insn(DisasContext *ctx)
+{
+ int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode));
+ int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
+
+ switch ((ctx->opcode >> 2) & 0x3) {
+ case NM_NOT16:
+ gen_logic(ctx, OPC_NOR, rt, rs, 0);
+ break;
+ case NM_AND16:
+ gen_logic(ctx, OPC_AND, rt, rt, rs);
+ break;
+ case NM_XOR16:
+ gen_logic(ctx, OPC_XOR, rt, rt, rs);
+ break;
+ case NM_OR16:
+ gen_logic(ctx, OPC_OR, rt, rt, rs);
+ break;
+ }
+}
+
static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t op;
@@ -16585,6 +16606,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
case NM_P16C:
switch (ctx->opcode & 1) {
case NM_POOL16C_0:
+ gen_pool16c_nanomips_insn(ctx);
break;
case NM_LWXS16:
gen_ldxs(ctx, rt, rs, rd);
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 09/55] target/mips: Add emulation of nanoMIPS 16-bit save and restore instructions
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (7 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 08/55] target/mips: Add emulation of nanoMIPS 16-bit logic instructions Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 10/55] target/mips: Add emulation of some common nanoMIPS 32-bit instructions Aleksandar Markovic
` (45 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Yongbok Kim <yongbok.kim@mips.com>
Add emulation of SAVE16 and RESTORE.JRC16 instructions. Routines
gen_save(), gen_restore(), and gen_adjust_sp() are provided for this
purpose.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/translate.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4ef7df8..b76d8ec 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16510,6 +16510,65 @@ static inline int decode_gpr_gpr4_zero(int r)
#define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f)
+static void gen_adjust_sp(DisasContext *ctx, int u)
+{
+ TCGv tsp = tcg_temp_new();
+ gen_base_offset_addr(ctx, tsp, 29, u);
+ gen_store_gpr(tsp, 29);
+ tcg_temp_free(tsp);
+}
+
+static void gen_save(DisasContext *ctx, uint8_t rt, uint8_t count,
+ uint8_t gp, uint16_t u)
+{
+ int counter = 0;
+ TCGv va = tcg_temp_new();
+ TCGv t0 = tcg_temp_new();
+
+ while (counter != count) {
+ bool use_gp = gp && (counter == count - 1);
+ int this_rt = use_gp ? 28 : (rt & 0x10) | ((rt + counter) & 0x1f);
+ int this_offset = -((counter + 1) << 2);
+ gen_base_offset_addr(ctx, va, 29, this_offset);
+ gen_load_gpr(t0, this_rt);
+ tcg_gen_qemu_st_tl(t0, va, ctx->mem_idx,
+ (MO_TEUL | ctx->default_tcg_memop_mask));
+ counter++;
+ }
+
+ /* adjust stack pointer */
+ gen_adjust_sp(ctx, -u);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(va);
+}
+
+static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count,
+ uint8_t gp, uint16_t u)
+{
+ int counter = 0;
+ TCGv va = tcg_temp_new();
+ TCGv t0 = tcg_temp_new();
+
+ while (counter != count) {
+ bool use_gp = gp && (counter == count - 1);
+ int this_rt = use_gp ? 28 : (rt & 0x10) | ((rt + counter) & 0x1f);
+ int this_offset = u - ((counter + 1) << 2);
+ gen_base_offset_addr(ctx, va, 29, this_offset);
+ tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx, MO_TESL |
+ ctx->default_tcg_memop_mask);
+ tcg_gen_ext32s_tl(t0, t0);
+ gen_store_gpr(t0, this_rt);
+ counter++;
+ }
+
+ /* adjust stack pointer */
+ gen_adjust_sp(ctx, u);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(va);
+}
+
static void gen_pool16c_nanomips_insn(DisasContext *ctx)
{
int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode));
@@ -16860,6 +16919,21 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case NM_P16_SR:
+ {
+ int count = extract32(ctx->opcode, 0, 4);
+ int u = extract32(ctx->opcode, 4, 4) << 4;
+ int rt = 30 + extract32(ctx->opcode, 9, 1);
+
+ switch (extract32(ctx->opcode, 8, 1)) {
+ case NM_SAVE16:
+ gen_save(ctx, rt, count, 0, u);
+ break;
+ case NM_RESTORE_JRC16:
+ gen_restore(ctx, rt, count, 0, u);
+ gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0, 0);
+ break;
+ }
+ }
break;
case NM_MOVEP:
case NM_MOVEPREV:
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 10/55] target/mips: Add emulation of some common nanoMIPS 32-bit instructions
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (8 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 09/55] target/mips: Add emulation of nanoMIPS 16-bit save and restore instructions Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 19:38 ` Richard Henderson
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 11/55] target/mips: Add emulation of nanoMIPS 48-bit instructions Aleksandar Markovic
` (44 subsequent siblings)
54 siblings, 1 reply; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Yongbok Kim <yongbok.kim@mips.com>
Add emulation of SIGRIE, SYSCALL, BREAK, SDBBP, ADDIU, ADDIUPC,
ADDIUGP.W, LWGP, SWGP, ORI, XORI, ANDI, and other instructions.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 285 +++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 284 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index b76d8ec..0b69ceb 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16590,6 +16590,289 @@ static void gen_pool16c_nanomips_insn(DisasContext *ctx)
}
}
+static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
+{
+ uint16_t insn;
+ int rt, rs;
+ uint32_t op;
+
+ insn = cpu_lduw_code(env, ctx->base.pc_next + 2);
+ ctx->opcode = (ctx->opcode << 16) | insn;
+
+ rt = (ctx->opcode >> 21) & 0x1f;
+ rs = (ctx->opcode >> 16) & 0x1f;
+
+ op = (ctx->opcode >> 26) & 0x3f;
+ switch (op) {
+ case NM_P_ADDIU:
+ if (rt == 0) {
+ /* P.RI */
+ switch ((ctx->opcode >> 19) & 0x03) {
+ case NM_SIGRIE:
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ case NM_P_SYSCALL:
+ if (((ctx->opcode >> 18) & 0x01) == NM_SYSCALL) {
+ generate_exception_end(ctx, EXCP_SYSCALL);
+ } else {
+ generate_exception_end(ctx, EXCP_RI);
+ }
+ break;
+ case NM_BREAK:
+ generate_exception_end(ctx, EXCP_BREAK);
+ break;
+ case NM_SDBBP:
+ if (is_uhi(extract32(ctx->opcode, 0, 19))) {
+ gen_helper_do_semihosting(cpu_env);
+ } else {
+ if (ctx->hflags & MIPS_HFLAG_SBRI) {
+ generate_exception_end(ctx, EXCP_RI);
+ } else {
+ generate_exception_end(ctx, EXCP_DBp);
+ }
+ }
+ break;
+ }
+ } else {
+ uint16_t imm;
+ imm = (uint16_t) extract32(ctx->opcode, 0, 16);
+ if (rs != 0) {
+ tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm);
+ tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
+ } else {
+ tcg_gen_movi_tl(cpu_gpr[rt], imm);
+ }
+ }
+ break;
+ case NM_ADDIUPC:
+ if (rt != 0) {
+ int32_t offset = sextract32(ctx->opcode, 0, 1) << 21
+ | extract32(ctx->opcode, 1, 20) << 1;
+ target_long addr = addr_add(ctx, ctx->base.pc_next + 4, offset);
+ tcg_gen_movi_tl(cpu_gpr[rt], addr);
+ tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
+ }
+ break;
+ case NM_POOL32A:
+ break;
+ case NM_P_GP_W:
+ switch (ctx->opcode & 0x03) {
+ case NM_ADDIUGP_W:
+ if (rt != 0) {
+ uint32_t offset = extract32(ctx->opcode, 0, 21);
+ if (offset == 0) {
+ gen_load_gpr(cpu_gpr[rt], 28);
+ } else {
+ TCGv t0;
+ t0 = tcg_temp_new();
+ tcg_gen_movi_tl(t0, offset);
+ gen_op_addr_add(ctx, cpu_gpr[rt], cpu_gpr[28], t0);
+ tcg_temp_free(t0);
+ }
+ }
+ break;
+ case NM_LWGP:
+ gen_ld(ctx, OPC_LW, rt, 28, extract32(ctx->opcode, 2, 19) << 2);
+ break;
+ case NM_SWGP:
+ gen_st(ctx, OPC_SW, rt, 28, extract32(ctx->opcode, 2, 19) << 2);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ case NM_P48I:
+ return 6;
+ case NM_P_U12:
+ switch ((ctx->opcode >> 12) & 0x0f) {
+ case NM_ORI:
+ gen_logic_imm(ctx, OPC_ORI, rt, rs, extract32(ctx->opcode, 0, 12));
+ break;
+ case NM_XORI:
+ gen_logic_imm(ctx, OPC_XORI, rt, rs, extract32(ctx->opcode, 0, 12));
+ break;
+ case NM_ANDI:
+ gen_logic_imm(ctx, OPC_ANDI, rt, rs, extract32(ctx->opcode, 0, 12));
+ break;
+ case NM_P_SR:
+ switch ((ctx->opcode >> 20) & 1) {
+ case NM_PP_SR:
+ switch (ctx->opcode & 3) {
+ case NM_SAVE:
+ gen_save(ctx, rt, extract32(ctx->opcode, 16, 4),
+ (ctx->opcode >> 2) & 1,
+ extract32(ctx->opcode, 3, 9) << 3);
+ break;
+ case NM_RESTORE:
+ case NM_RESTORE_JRC:
+ gen_restore(ctx, rt, extract32(ctx->opcode, 16, 4),
+ (ctx->opcode >> 2) & 1,
+ extract32(ctx->opcode, 3, 9) << 3);
+ if ((ctx->opcode & 3) == NM_RESTORE_JRC) {
+ gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0, 0);
+ }
+ break;
+ }
+ break;
+ case NM_P_SR_F:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ case NM_SLTI:
+ gen_slt_imm(ctx, OPC_SLTI, rt, rs, extract32(ctx->opcode, 0, 12));
+ break;
+ case NM_SLTIU:
+ gen_slt_imm(ctx, OPC_SLTIU, rt, rs, extract32(ctx->opcode, 0, 12));
+ break;
+ case NM_SEQI:
+ {
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_local_new();
+ TCGLabel *l1 = gen_new_label();
+
+ gen_load_gpr(t0, rs);
+ tcg_gen_movi_tl(t1, extract32(ctx->opcode, 0, 12));
+ tcg_gen_movi_tl(t2, 0);
+ tcg_gen_brcond_tl(TCG_COND_NE, t0, t1, l1);
+ tcg_gen_movi_tl(t2, 1);
+ gen_set_label(l1);
+ gen_store_gpr(t2, rt);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+ }
+ break;
+ case NM_ADDIUNEG:
+ {
+ int16_t imm;
+ imm = (int16_t) extract32(ctx->opcode, 0, 12);
+ gen_arith_imm(ctx, OPC_ADDIU, rt, rs, -imm);
+ }
+ break;
+ case NM_P_SHIFT:
+ {
+ int shift = extract32(ctx->opcode, 0, 5);
+ switch ((ctx->opcode >> 5) & 0x0f) {
+ case NM_P_SLL:
+ if (rt == 0 && shift == 0) {
+ /* NOP */
+ } else if (rt == 0 && shift == 3) {
+ /* EHB treat as NOP */
+ } else if (rt == 0 && shift == 5) {
+ /* PAUSE */
+ if (ctx->hflags & MIPS_HFLAG_BMASK) {
+ generate_exception_end(ctx, EXCP_RI);
+ }
+ } else if (rt == 0 && shift == 6) {
+ /* SYNC */
+ check_insn(ctx, ISA_MIPS2);
+ /* Treat as NOP. */
+ } else {
+ /* SLL */
+ gen_shift_imm(ctx, OPC_SLL, rt, rs,
+ extract32(ctx->opcode, 0, 5));
+ }
+ break;
+ case NM_SRL:
+ gen_shift_imm(ctx, OPC_SRL, rt, rs,
+ extract32(ctx->opcode, 0, 5));
+ break;
+ case NM_SRA:
+ gen_shift_imm(ctx, OPC_SRA, rt, rs,
+ extract32(ctx->opcode, 0, 5));
+ break;
+ case NM_ROTR:
+ gen_shift_imm(ctx, OPC_ROTR, rt, rs,
+ extract32(ctx->opcode, 0, 5));
+ break;
+ }
+ }
+ break;
+ case NM_P_ROTX:
+ break;
+ case NM_P_INS:
+ switch (((ctx->opcode >> 10) & 2) | ((ctx->opcode >> 5) & 1)) {
+ case NM_INS:
+ gen_bitops(ctx, OPC_INS, rt, rs, extract32(ctx->opcode, 0, 5),
+ extract32(ctx->opcode, 6, 5));
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ case NM_P_EXT:
+ switch (((ctx->opcode >> 10) & 2) | ((ctx->opcode >> 5) & 1)) {
+ case NM_EXT:
+ gen_bitops(ctx, OPC_EXT, rt, rs, extract32(ctx->opcode, 0, 5),
+ extract32(ctx->opcode, 6, 5));
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ case NM_POOL32F:
+ break;
+ case NM_POOL32S:
+ break;
+ case NM_P_LUI:
+ switch ((ctx->opcode >> 1) & 1) {
+ case NM_LUI:
+ if (rt != 0) {
+ tcg_gen_movi_tl(cpu_gpr[rt],
+ sextract32(ctx->opcode, 0, 1) << 31 |
+ extract32(ctx->opcode, 2, 10) << 21 |
+ extract32(ctx->opcode, 12, 9) << 12);
+ }
+ break;
+ case NM_ALUIPC:
+ if (rt != 0) {
+ int offset = sextract32(ctx->opcode, 0, 1) << 31 |
+ extract32(ctx->opcode, 2, 10) << 21 |
+ extract32(ctx->opcode, 12, 9) << 12;
+ target_long addr;
+ addr = ~0xFFF & addr_add(ctx, ctx->base.pc_next + 4, offset);
+ tcg_gen_movi_tl(cpu_gpr[rt], addr);
+ }
+ break;
+ }
+ break;
+ case NM_P_GP_BH:
+ break;
+ case NM_P_LS_U12:
+ break;
+ case NM_P_LS_S9:
+ break;
+ case NM_MOVE_BALC:
+ break;
+ case NM_P_BAL:
+ break;
+ case NM_P_J:
+ break;
+ case NM_P_BR1:
+ break;
+ case NM_P_BR2:
+ break;
+ case NM_P_BRI:
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ return 4;
+}
+
static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t op;
@@ -16971,7 +17254,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
default:
- break;
+ return decode_nanomips_32_48_opc(env, ctx);
}
return 2;
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v4 10/55] target/mips: Add emulation of some common nanoMIPS 32-bit instructions
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 10/55] target/mips: Add emulation of some common nanoMIPS 32-bit instructions Aleksandar Markovic
@ 2018-07-24 19:38 ` Richard Henderson
0 siblings, 0 replies; 65+ messages in thread
From: Richard Henderson @ 2018-07-24 19:38 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien, amarkovic,
smarkovic, pjovanovic, pburton
On 07/24/2018 10:31 AM, Aleksandar Markovic wrote:
> + case NM_ADDIUPC:
> + if (rt != 0) {
> + int32_t offset = sextract32(ctx->opcode, 0, 1) << 21
> + | extract32(ctx->opcode, 1, 20) << 1;
> + target_long addr = addr_add(ctx, ctx->base.pc_next + 4, offset);
> + tcg_gen_movi_tl(cpu_gpr[rt], addr);
> + tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
> + }
I really need you to address all of the comments from a round of review before
posting the next round.
I'm going to stop now, let you address all of the v3 review and then post a v5.
r~
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v4 11/55] target/mips: Add emulation of nanoMIPS 48-bit instructions
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (9 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 10/55] target/mips: Add emulation of some common nanoMIPS 32-bit instructions Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 12/55] target/mips: Add emulation of nanoMIPS FP instructions Aleksandar Markovic
` (43 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Yongbok Kim <yongbok.kim@mips.com>
Add emulation of LI48, ADDIU48, ADDIUGP48, ADDIUPC48, LWPC48, and
SWPC48 instructions.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 66 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 0b69ceb..f5f722d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16684,6 +16684,72 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case NM_P48I:
+ insn = cpu_lduw_code(env, ctx->base.pc_next + 4);
+ switch ((ctx->opcode >> 16) & 0x1f) {
+ case NM_LI48:
+ if (rt != 0) {
+ tcg_gen_movi_tl(cpu_gpr[rt],
+ extract32(ctx->opcode, 0, 16) | insn << 16);
+ }
+ break;
+ case NM_ADDIU48:
+ if (rt != 0) {
+ tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rt],
+ extract32(ctx->opcode, 0, 16) | insn << 16);
+ tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
+ }
+ break;
+ case NM_ADDIUGP48:
+ if (rt != 0) {
+ tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[28],
+ extract32(ctx->opcode, 0, 16) | insn << 16);
+ tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
+ }
+ break;
+ case NM_ADDIUPC48:
+ if (rt != 0) {
+ int32_t offset = extract32(ctx->opcode, 0, 16) | insn << 16;
+ target_long addr = addr_add(ctx, ctx->base.pc_next + 6, offset);
+
+ tcg_gen_movi_tl(cpu_gpr[rt], addr);
+ tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
+ }
+ break;
+ case NM_LWPC48:
+ if (rt != 0) {
+ TCGv t0;
+ t0 = tcg_temp_new();
+
+ int32_t offset = extract32(ctx->opcode, 0, 16) | insn << 16;
+ target_long addr = addr_add(ctx, ctx->base.pc_next + 6, offset);
+
+ tcg_gen_movi_tl(t0, addr);
+ tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, MO_TESL);
+ tcg_temp_free(t0);
+ }
+ break;
+ case NM_SWPC48:
+ {
+ TCGv t0, t1;
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+
+ int32_t offset = extract32(ctx->opcode, 0, 16) | insn << 16;
+ target_long addr = addr_add(ctx, ctx->base.pc_next + 6, offset);
+
+ tcg_gen_movi_tl(t0, addr);
+ gen_load_gpr(t1, rt);
+
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
return 6;
case NM_P_U12:
switch ((ctx->opcode >> 12) & 0x0f) {
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 12/55] target/mips: Add emulation of nanoMIPS FP instructions
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (10 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 11/55] target/mips: Add emulation of nanoMIPS 48-bit instructions Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 13/55] target/mips: Add emulation of misc nanoMIPS instructions (pool32a0) Aleksandar Markovic
` (42 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Yongbok Kim <yongbok.kim@mips.com>
Add emulation of basic floating point arithmetic for nanoMIPS.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/translate.c | 300 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 300 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f5f722d..90b1a1d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16590,6 +16590,305 @@ static void gen_pool16c_nanomips_insn(DisasContext *ctx)
}
}
+static void gen_pool32f_nanomips_insn(DisasContext *ctx)
+{
+ int rt, rs, rd;
+
+ rt = extract32(ctx->opcode, 21, 5);
+ rs = extract32(ctx->opcode, 16, 5);
+ rd = extract32(ctx->opcode, 11, 5);
+
+ if (!(ctx->CP0_Config1 & (1 << CP0C1_FP))) {
+ generate_exception_end(ctx, EXCP_RI);
+ return;
+ }
+ check_cp1_enabled(ctx);
+ switch (extract32(ctx->opcode, 0, 3)) {
+ case NM_POOL32F_0:
+ switch (extract32(ctx->opcode, 3, 7)) {
+ case NM_RINT_S:
+ gen_farith(ctx, OPC_RINT_S, 0, rt, rs, 0);
+ break;
+ case NM_RINT_D:
+ gen_farith(ctx, OPC_RINT_D, 0, rt, rs, 0);
+ break;
+ case NM_CLASS_S:
+ gen_farith(ctx, OPC_CLASS_S, 0, rt, rs, 0);
+ break;
+ case NM_CLASS_D:
+ gen_farith(ctx, OPC_CLASS_D, 0, rt, rs, 0);
+ break;
+ case NM_ADD_S:
+ gen_farith(ctx, OPC_ADD_S, rt, rs, rd, 0);
+ break;
+ case NM_ADD_D:
+ gen_farith(ctx, OPC_ADD_D, rt, rs, rd, 0);
+ break;
+ case NM_SUB_S:
+ gen_farith(ctx, OPC_SUB_S, rt, rs, rd, 0);
+ break;
+ case NM_SUB_D:
+ gen_farith(ctx, OPC_SUB_D, rt, rs, rd, 0);
+ break;
+ case NM_MUL_S:
+ gen_farith(ctx, OPC_MUL_S, rt, rs, rd, 0);
+ break;
+ case NM_MUL_D:
+ gen_farith(ctx, OPC_MUL_D, rt, rs, rd, 0);
+ break;
+ case NM_DIV_S:
+ gen_farith(ctx, OPC_DIV_S, rt, rs, rd, 0);
+ break;
+ case NM_DIV_D:
+ gen_farith(ctx, OPC_DIV_D, rt, rs, rd, 0);
+ break;
+ case NM_SELEQZ_S:
+ gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs);
+ break;
+ case NM_SELEQZ_D:
+ gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs);
+ break;
+ case NM_SELNEZ_S:
+ gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs);
+ break;
+ case NM_SELNEZ_D:
+ gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs);
+ break;
+ case NM_SEL_S:
+ gen_sel_s(ctx, OPC_SEL_S, rd, rt, rs);
+ break;
+ case NM_SEL_D:
+ gen_sel_d(ctx, OPC_SEL_D, rd, rt, rs);
+ break;
+ case NM_MADDF_S:
+ gen_farith(ctx, OPC_MADDF_S, rt, rs, rd, 0);
+ break;
+ case NM_MADDF_D:
+ gen_farith(ctx, OPC_MADDF_D, rt, rs, rd, 0);
+ break;
+ case NM_MSUBF_S:
+ gen_farith(ctx, OPC_MSUBF_S, rt, rs, rd, 0);
+ break;
+ case NM_MSUBF_D:
+ gen_farith(ctx, OPC_MSUBF_D, rt, rs, rd, 0);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ case NM_POOL32F_3:
+ switch (extract32(ctx->opcode, 3, 3)) {
+ case NM_MIN_FMT:
+ switch (extract32(ctx->opcode, 9, 1)) {
+ case FMT_SDPS_S:
+ gen_farith(ctx, OPC_MIN_S, rt, rs, rd, 0);
+ break;
+ case FMT_SDPS_D:
+ gen_farith(ctx, OPC_MIN_D, rt, rs, rd, 0);
+ break;
+ }
+ break;
+ case NM_MAX_FMT:
+ switch (extract32(ctx->opcode, 9, 1)) {
+ case FMT_SDPS_S:
+ gen_farith(ctx, OPC_MAX_S, rt, rs, rd, 0);
+ break;
+ case FMT_SDPS_D:
+ gen_farith(ctx, OPC_MAX_D, rt, rs, rd, 0);
+ break;
+ }
+ break;
+ case NM_MINA_FMT:
+ switch (extract32(ctx->opcode, 9, 1)) {
+ case FMT_SDPS_S:
+ gen_farith(ctx, OPC_MINA_S, rt, rs, rd, 0);
+ break;
+ case FMT_SDPS_D:
+ gen_farith(ctx, OPC_MINA_D, rt, rs, rd, 0);
+ break;
+ }
+ break;
+ case NM_MAXA_FMT:
+ switch (extract32(ctx->opcode, 9, 1)) {
+ case FMT_SDPS_S:
+ gen_farith(ctx, OPC_MAXA_S, rt, rs, rd, 0);
+ break;
+ case FMT_SDPS_D:
+ gen_farith(ctx, OPC_MAXA_D, rt, rs, rd, 0);
+ break;
+ }
+ break;
+ case NM_POOL32FXF:
+ switch (extract32(ctx->opcode, 6, 8)) {
+ case NM_CFC1:
+ gen_cp1(ctx, OPC_CFC1, rt, rs);
+ break;
+ case NM_CTC1:
+ gen_cp1(ctx, OPC_CTC1, rt, rs);
+ break;
+ case NM_MFC1:
+ gen_cp1(ctx, OPC_MFC1, rt, rs);
+ break;
+ case NM_MTC1:
+ gen_cp1(ctx, OPC_MTC1, rt, rs);
+ break;
+ case NM_MFHC1:
+ gen_cp1(ctx, OPC_MFHC1, rt, rs);
+ break;
+ case NM_MTHC1:
+ gen_cp1(ctx, OPC_MTHC1, rt, rs);
+ break;
+ case NM_CVT_S_PL:
+ gen_farith(ctx, OPC_CVT_S_PL, -1, rs, rt, 0);
+ break;
+ case NM_CVT_S_PU:
+ gen_farith(ctx, OPC_CVT_S_PU, -1, rs, rt, 0);
+ break;
+ default:
+ switch (extract32(ctx->opcode, 6, 9)) {
+ case NM_CVT_L_S:
+ gen_farith(ctx, OPC_CVT_L_S, -1, rs, rt, 0);
+ break;
+ case NM_CVT_L_D:
+ gen_farith(ctx, OPC_CVT_L_D, -1, rs, rt, 0);
+ break;
+ case NM_CVT_W_S:
+ gen_farith(ctx, OPC_CVT_W_S, -1, rs, rt, 0);
+ break;
+ case NM_CVT_W_D:
+ gen_farith(ctx, OPC_CVT_W_D, -1, rs, rt, 0);
+ break;
+ case NM_RSQRT_S:
+ gen_farith(ctx, OPC_RSQRT_S, -1, rs, rt, 0);
+ break;
+ case NM_RSQRT_D:
+ gen_farith(ctx, OPC_RSQRT_D, -1, rs, rt, 0);
+ break;
+ case NM_SQRT_S:
+ gen_farith(ctx, OPC_SQRT_S, -1, rs, rt, 0);
+ break;
+ case NM_SQRT_D:
+ gen_farith(ctx, OPC_SQRT_D, -1, rs, rt, 0);
+ break;
+ case NM_RECIP_S:
+ gen_farith(ctx, OPC_RECIP_S, -1, rs, rt, 0);
+ break;
+ case NM_RECIP_D:
+ gen_farith(ctx, OPC_RECIP_D, -1, rs, rt, 0);
+ break;
+ case NM_FLOOR_L_S:
+ gen_farith(ctx, OPC_FLOOR_L_S, -1, rs, rt, 0);
+ break;
+ case NM_FLOOR_L_D:
+ gen_farith(ctx, OPC_FLOOR_L_D, -1, rs, rt, 0);
+ break;
+ case NM_FLOOR_W_S:
+ gen_farith(ctx, OPC_FLOOR_W_S, -1, rs, rt, 0);
+ break;
+ case NM_FLOOR_W_D:
+ gen_farith(ctx, OPC_FLOOR_W_D, -1, rs, rt, 0);
+ break;
+ case NM_CEIL_L_S:
+ gen_farith(ctx, OPC_CEIL_L_S, -1, rs, rt, 0);
+ break;
+ case NM_CEIL_L_D:
+ gen_farith(ctx, OPC_CEIL_L_D, -1, rs, rt, 0);
+ break;
+ case NM_CEIL_W_S:
+ gen_farith(ctx, OPC_CEIL_W_S, -1, rs, rt, 0);
+ break;
+ case NM_CEIL_W_D:
+ gen_farith(ctx, OPC_CEIL_W_D, -1, rs, rt, 0);
+ break;
+ case NM_TRUNC_L_S:
+ gen_farith(ctx, OPC_TRUNC_L_S, -1, rs, rt, 0);
+ break;
+ case NM_TRUNC_L_D:
+ gen_farith(ctx, OPC_TRUNC_L_D, -1, rs, rt, 0);
+ break;
+ case NM_TRUNC_W_S:
+ gen_farith(ctx, OPC_TRUNC_W_S, -1, rs, rt, 0);
+ break;
+ case NM_TRUNC_W_D:
+ gen_farith(ctx, OPC_TRUNC_W_D, -1, rs, rt, 0);
+ break;
+ case NM_ROUND_L_S:
+ gen_farith(ctx, OPC_ROUND_L_S, -1, rs, rt, 0);
+ break;
+ case NM_ROUND_L_D:
+ gen_farith(ctx, OPC_ROUND_L_D, -1, rs, rt, 0);
+ break;
+ case NM_ROUND_W_S:
+ gen_farith(ctx, OPC_ROUND_W_S, -1, rs, rt, 0);
+ break;
+ case NM_ROUND_W_D:
+ gen_farith(ctx, OPC_ROUND_W_D, -1, rs, rt, 0);
+ break;
+ case NM_MOV_S:
+ gen_farith(ctx, OPC_MOV_S, -1, rs, rt, 0);
+ break;
+ case NM_MOV_D:
+ gen_farith(ctx, OPC_MOV_D, -1, rs, rt, 0);
+ break;
+ case NM_ABS_S:
+ gen_farith(ctx, OPC_ABS_S, -1, rs, rt, 0);
+ break;
+ case NM_ABS_D:
+ gen_farith(ctx, OPC_ABS_D, -1, rs, rt, 0);
+ break;
+ case NM_NEG_S:
+ gen_farith(ctx, OPC_NEG_S, -1, rs, rt, 0);
+ break;
+ case NM_NEG_D:
+ gen_farith(ctx, OPC_NEG_D, -1, rs, rt, 0);
+ break;
+ case NM_CVT_D_S:
+ gen_farith(ctx, OPC_CVT_D_S, -1, rs, rt, 0);
+ break;
+ case NM_CVT_D_W:
+ gen_farith(ctx, OPC_CVT_D_W, -1, rs, rt, 0);
+ break;
+ case NM_CVT_D_L:
+ gen_farith(ctx, OPC_CVT_D_L, -1, rs, rt, 0);
+ break;
+ case NM_CVT_S_D:
+ gen_farith(ctx, OPC_CVT_S_D, -1, rs, rt, 0);
+ break;
+ case NM_CVT_S_W:
+ gen_farith(ctx, OPC_CVT_S_W, -1, rs, rt, 0);
+ break;
+ case NM_CVT_S_L:
+ gen_farith(ctx, OPC_CVT_S_L, -1, rs, rt, 0);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case NM_POOL32F_5:
+ switch (extract32(ctx->opcode, 3, 3)) {
+ case NM_CMP_CONDN_S:
+ gen_r6_cmp_s(ctx, extract32(ctx->opcode, 6, 5), rt, rs, rd);
+ break;
+ case NM_CMP_CONDN_D:
+ gen_r6_cmp_d(ctx, extract32(ctx->opcode, 6, 5), rt, rs, rd);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+}
+
static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
{
uint16_t insn;
@@ -16889,6 +17188,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case NM_POOL32F:
+ gen_pool32f_nanomips_insn(ctx);
break;
case NM_POOL32S:
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 13/55] target/mips: Add emulation of misc nanoMIPS instructions (pool32a0)
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (11 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 12/55] target/mips: Add emulation of nanoMIPS FP instructions Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 14/55] target/mips: Add emulation of misc nanoMIPS instructions (pool32axf) Aleksandar Markovic
` (41 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Yongbok Kim <yongbok.kim@mips.com>
Add emulation of nanoMIPS instructions that are situated in pool32a0.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 190 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 190 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 90b1a1d..e5ebdb9 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16590,6 +16590,186 @@ static void gen_pool16c_nanomips_insn(DisasContext *ctx)
}
}
+static void gen_pool32a0_nanomips_insn(DisasContext *ctx)
+{
+ int rt = (ctx->opcode >> 21) & 0x1f;
+ int rs = (ctx->opcode >> 16) & 0x1f;
+ int rd = (ctx->opcode >> 11) & 0x1f;
+
+ switch ((ctx->opcode >> 3) & 0x7f) {
+ case NM_P_TRAP:
+ switch ((ctx->opcode >> 10) & 0x1) {
+ case NM_TEQ:
+ gen_trap(ctx, OPC_TEQ, rs, rt, -1);
+ break;
+ case NM_TNE:
+ gen_trap(ctx, OPC_TNE, rs, rt, -1);
+ break;
+ }
+ break;
+ case NM_RDHWR:
+ gen_rdhwr(ctx, rt, rs, extract32(ctx->opcode, 11, 3));
+ break;
+ case NM_SEB:
+ gen_bshfl(ctx, OPC_SEB, rs, rt);
+ break;
+ case NM_SEH:
+ gen_bshfl(ctx, OPC_SEH, rs, rt);
+ break;
+ case NM_SLLV:
+ gen_shift(ctx, OPC_SLLV, rd, rt, rs);
+ break;
+ case NM_SRLV:
+ gen_shift(ctx, OPC_SRLV, rd, rt, rs);
+ break;
+ case NM_SRAV:
+ gen_shift(ctx, OPC_SRAV, rd, rt, rs);
+ break;
+ case NM_ROTRV:
+ gen_shift(ctx, OPC_ROTRV, rd, rt, rs);
+ break;
+ case NM_ADD:
+ gen_arith(ctx, OPC_ADD, rd, rs, rt);
+ break;
+ case NM_ADDU:
+ gen_arith(ctx, OPC_ADDU, rd, rs, rt);
+ break;
+ case NM_SUB:
+ gen_arith(ctx, OPC_SUB, rd, rs, rt);
+ break;
+ case NM_SUBU:
+ gen_arith(ctx, OPC_SUBU, rd, rs, rt);
+ break;
+ case NM_P_CMOVE:
+ switch ((ctx->opcode >> 10) & 1) {
+ case NM_MOVZ:
+ gen_cond_move(ctx, OPC_MOVZ, rd, rs, rt);
+ break;
+ case NM_MOVN:
+ gen_cond_move(ctx, OPC_MOVN, rd, rs, rt);
+ break;
+ }
+ break;
+ case NM_AND:
+ gen_logic(ctx, OPC_AND, rd, rs, rt);
+ break;
+ case NM_OR:
+ gen_logic(ctx, OPC_OR, rd, rs, rt);
+ break;
+ case NM_NOR:
+ gen_logic(ctx, OPC_NOR, rd, rs, rt);
+ break;
+ case NM_XOR:
+ gen_logic(ctx, OPC_XOR, rd, rs, rt);
+ break;
+ case NM_SLT:
+ gen_slt(ctx, OPC_SLT, rd, rs, rt);
+ break;
+ case NM_P_SLTU:
+ if (rd == 0) {
+ /* P_DVP */
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ switch ((ctx->opcode >> 10) & 1) {
+ case NM_DVP:
+ if (ctx->vp) {
+ check_cp0_enabled(ctx);
+ gen_helper_dvp(t0, cpu_env);
+ gen_store_gpr(t0, rt);
+ }
+ break;
+ case NM_EVP:
+ if (ctx->vp) {
+ check_cp0_enabled(ctx);
+ gen_helper_evp(t0, cpu_env);
+ gen_store_gpr(t0, rt);
+ }
+ break;
+ }
+ tcg_temp_free(t0);
+#endif
+ } else {
+ gen_slt(ctx, OPC_SLTU, rd, rs, rt);
+ }
+ break;
+ case NM_SOV:
+ {
+ TCGv t0 = tcg_temp_local_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+ TCGLabel *l1 = gen_new_label();
+
+ gen_load_gpr(t1, rs);
+ gen_load_gpr(t2, rt);
+ tcg_gen_add_tl(t0, t1, t2);
+ tcg_gen_ext32s_tl(t0, t0);
+ tcg_gen_xor_tl(t1, t1, t2);
+ tcg_gen_xor_tl(t2, t0, t2);
+ tcg_gen_andc_tl(t1, t2, t1);
+
+ tcg_gen_movi_tl(t0, 0);
+ tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
+ /* operands of same sign, result different sign */
+
+ tcg_gen_movi_tl(t0, 1);
+ gen_set_label(l1);
+ gen_store_gpr(t0, rd);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+ }
+ break;
+ case NM_MUL:
+ gen_r6_muldiv(ctx, R6_OPC_MUL, rd, rs, rt);
+ break;
+ case NM_MUH:
+ gen_r6_muldiv(ctx, R6_OPC_MUH, rd, rs, rt);
+ break;
+ case NM_MULU:
+ gen_r6_muldiv(ctx, R6_OPC_MULU, rd, rs, rt);
+ break;
+ case NM_MUHU:
+ gen_r6_muldiv(ctx, R6_OPC_MUHU, rd, rs, rt);
+ break;
+ case NM_DIV:
+ gen_r6_muldiv(ctx, R6_OPC_DIV, rd, rs, rt);
+ break;
+ case NM_MOD:
+ gen_r6_muldiv(ctx, R6_OPC_MOD, rd, rs, rt);
+ break;
+ case NM_DIVU:
+ gen_r6_muldiv(ctx, R6_OPC_DIVU, rd, rs, rt);
+ break;
+ case NM_MODU:
+ gen_r6_muldiv(ctx, R6_OPC_MODU, rd, rs, rt);
+ break;
+#ifndef CONFIG_USER_ONLY
+ case NM_MFC0:
+ check_cp0_enabled(ctx);
+ if (rt == 0) {
+ /* Treat as NOP. */
+ break;
+ }
+ gen_mfc0(ctx, cpu_gpr[rt], rs, (ctx->opcode >> 11) & 0x7);
+ break;
+ case NM_MTC0:
+ check_cp0_enabled(ctx);
+ {
+ TCGv t0 = tcg_temp_new();
+
+ gen_load_gpr(t0, rt);
+ gen_mtc0(ctx, t0, rs, (ctx->opcode >> 11) & 0x7);
+ tcg_temp_free(t0);
+ }
+ break;
+#endif
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+}
+
static void gen_pool32f_nanomips_insn(DisasContext *ctx)
{
int rt, rs, rd;
@@ -16954,6 +17134,16 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case NM_POOL32A:
+ switch (ctx->opcode & 0x07) {
+ case NM_POOL32A0:
+ gen_pool32a0_nanomips_insn(ctx);
+ break;
+ case NM_POOL32A7:
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
break;
case NM_P_GP_W:
switch (ctx->opcode & 0x03) {
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 14/55] target/mips: Add emulation of misc nanoMIPS instructions (pool32axf)
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (12 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 13/55] target/mips: Add emulation of misc nanoMIPS instructions (pool32a0) Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 15/55] target/mips: Add emulation of misc nanoMIPS instructions (pool p_lsx) Aleksandar Markovic
` (40 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Yongbok Kim <yongbok.kim@mips.com>
Add emulation of misc nanoMIPS instructions situated in pool32axf.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/translate.c | 95 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 95 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index e5ebdb9..24b0a54 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16770,6 +16770,93 @@ static void gen_pool32a0_nanomips_insn(DisasContext *ctx)
}
}
+static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
+{
+ int rt = (ctx->opcode >> 21) & 0x1f;
+ int rs = (ctx->opcode >> 16) & 0x1f;
+
+ switch ((ctx->opcode >> 6) & 0x07) {
+ case NM_POOL32AXF_4:
+ case NM_POOL32AXF_5:
+ switch ((ctx->opcode >> 9) & 0x7f) {
+ case NM_CLO:
+ gen_cl(ctx, OPC_CLO, rt, rs);
+ break;
+ case NM_CLZ:
+ gen_cl(ctx, OPC_CLZ, rt, rs);
+ break;
+#ifndef CONFIG_USER_ONLY
+ case NM_TLBP:
+ gen_cp0(env, ctx, OPC_TLBP, 0, 0);
+ break;
+ case NM_TLBR:
+ gen_cp0(env, ctx, OPC_TLBR, 0, 0);
+ break;
+ case NM_TLBWI:
+ gen_cp0(env, ctx, OPC_TLBWI, 0, 0);
+ break;
+ case NM_TLBWR:
+ gen_cp0(env, ctx, OPC_TLBWR, 0, 0);
+ break;
+ case NM_TLBINV:
+ gen_cp0(env, ctx, OPC_TLBINV, 0, 0);
+ break;
+ case NM_TLBINVF:
+ gen_cp0(env, ctx, OPC_TLBINVF, 0, 0);
+ break;
+ case NM_DI:
+ check_cp0_enabled(ctx);
+ {
+ TCGv t0 = tcg_temp_new();
+
+ save_cpu_state(ctx, 1);
+ gen_helper_di(t0, cpu_env);
+ gen_store_gpr(t0, rt);
+ /* Stop translation as we may have switched the execution mode */
+ ctx->base.is_jmp = DISAS_STOP;
+ tcg_temp_free(t0);
+ }
+ break;
+ case NM_EI:
+ check_cp0_enabled(ctx);
+ {
+ TCGv t0 = tcg_temp_new();
+
+ save_cpu_state(ctx, 1);
+ gen_helper_ei(t0, cpu_env);
+ gen_store_gpr(t0, rt);
+ /* Stop translation as we may have switched the execution mode */
+ ctx->base.is_jmp = DISAS_STOP;
+ tcg_temp_free(t0);
+ }
+ break;
+ case NM_RDPGPR:
+ gen_load_srsgpr(rs, rt);
+ break;
+ case NM_WRPGPR:
+ gen_store_srsgpr(rs, rt);
+ break;
+ case NM_WAIT:
+ gen_cp0(env, ctx, OPC_WAIT, 0, 0);
+ break;
+ case NM_DERET:
+ gen_cp0(env, ctx, OPC_DERET, 0, 0);
+ break;
+ case NM_ERETX:
+ gen_cp0(env, ctx, OPC_ERET, 0, 0);
+ break;
+#endif
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+}
+
static void gen_pool32f_nanomips_insn(DisasContext *ctx)
{
int rt, rs, rd;
@@ -17139,6 +17226,14 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_pool32a0_nanomips_insn(ctx);
break;
case NM_POOL32A7:
+ switch ((ctx->opcode >> 3) & 0x07) {
+ case NM_POOL32AXF:
+ gen_pool32axf_nanomips_insn(env, ctx);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
break;
default:
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 15/55] target/mips: Add emulation of misc nanoMIPS instructions (pool p_lsx)
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (13 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 14/55] target/mips: Add emulation of misc nanoMIPS instructions (pool32axf) Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 16/55] target/mips: Implement emulation of nanoMIPS ROTX instruction Aleksandar Markovic
` (39 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Yongbok Kim <yongbok.kim@mips.com>
Add emulation of nanoMIPS instructions situated in pool p_lsx, and
emulation of LSA instruction as well.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 139 +++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 138 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 24b0a54..1aafb74 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16857,6 +16857,132 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
}
}
+
+static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
+{
+ TCGv t0, t1;
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ tcg_gen_movi_tl(t1, 0);
+ if (rs == 0) {
+ tcg_gen_movi_tl(t0, 0);
+ } else {
+ gen_load_gpr(t0, rs);
+ }
+ if (rt == 0) {
+ tcg_gen_movi_tl(t1, 0);
+ } else {
+ gen_load_gpr(t1, rt);
+ }
+ if (((ctx->opcode >> 6) & 1) == 1) {
+ /* PP.LSXS instructions require shifting */
+ switch ((ctx->opcode >> 7) & 0xf) {
+ case NM_LHXS:
+ case NM_SHXS:
+ case NM_LHUXS:
+ tcg_gen_shli_tl(t0, t0, 1);
+ break;
+ case NM_LWXS:
+ case NM_SWXS:
+ case NM_LWC1XS:
+ case NM_SWC1XS:
+ tcg_gen_shli_tl(t0, t0, 2);
+ break;
+ case NM_LDC1XS:
+ case NM_SDC1XS:
+ tcg_gen_shli_tl(t0, t0, 3);
+ break;
+ }
+ }
+ gen_op_addr_add(ctx, t0, t0, t1);
+
+ switch ((ctx->opcode >> 7) & 0xf) {
+ case NM_LBX:
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
+ MO_SB);
+ gen_store_gpr(t0, rd);
+ break;
+ case NM_LHX:
+ /*case NM_LHXS:*/
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
+ MO_TESW);
+ gen_store_gpr(t0, rd);
+ break;
+ case NM_LWX:
+ /*case NM_LWXS:*/
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
+ MO_TESL);
+ gen_store_gpr(t0, rd);
+ break;
+ case NM_LBUX:
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
+ MO_UB);
+ gen_store_gpr(t0, rd);
+ break;
+ case NM_LHUX:
+ /*case NM_LHUXS:*/
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
+ MO_TEUW);
+ gen_store_gpr(t0, rd);
+ break;
+ case NM_SBX:
+ gen_load_gpr(t1, rd);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
+ MO_8);
+ break;
+ case NM_SHX:
+ /*case NM_SHXS:*/
+ gen_load_gpr(t1, rd);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
+ MO_TEUW);
+ break;
+ case NM_SWX:
+ /*case NM_SWXS:*/
+ gen_load_gpr(t1, rd);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
+ MO_TEUL);
+ break;
+ case NM_LWC1X:
+ /*case NM_LWC1XS:*/
+ case NM_LDC1X:
+ /*case NM_LDC1XS:*/
+ case NM_SWC1X:
+ /*case NM_SWC1XS:*/
+ case NM_SDC1X:
+ /*case NM_SDC1XS:*/
+ if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
+ check_cp1_enabled(ctx);
+ switch ((ctx->opcode >> 7) & 0xf) {
+ case NM_LWC1X:
+ /*case NM_LWC1XS:*/
+ gen_flt_ldst(ctx, OPC_LWC1, rd, t0);
+ break;
+ case NM_LDC1X:
+ /*case NM_LDC1XS:*/
+ gen_flt_ldst(ctx, OPC_LDC1, rd, t0);
+ break;
+ case NM_SWC1X:
+ /*case NM_SWC1XS:*/
+ gen_flt_ldst(ctx, OPC_SWC1, rd, t0);
+ break;
+ case NM_SDC1X:
+ /*case NM_SDC1XS:*/
+ gen_flt_ldst(ctx, OPC_SDC1, rd, t0);
+ break;
+ }
+ } else {
+ generate_exception_err(ctx, EXCP_CpU, 1);
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
static void gen_pool32f_nanomips_insn(DisasContext *ctx)
{
int rt, rs, rd;
@@ -17159,7 +17285,7 @@ static void gen_pool32f_nanomips_insn(DisasContext *ctx)
static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
{
uint16_t insn;
- int rt, rs;
+ int rt, rs, rd;
uint32_t op;
insn = cpu_lduw_code(env, ctx->base.pc_next + 2);
@@ -17167,6 +17293,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
rt = (ctx->opcode >> 21) & 0x1f;
rs = (ctx->opcode >> 16) & 0x1f;
+ rd = (ctx->opcode >> 11) & 0x1f;
op = (ctx->opcode >> 26) & 0x3f;
switch (op) {
@@ -17227,6 +17354,16 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case NM_POOL32A7:
switch ((ctx->opcode >> 3) & 0x07) {
+ case NM_P_LSX:
+ gen_p_lsx(ctx, rd, rs, rt);
+ break;
+ case NM_LSA:
+ /* In nanoMIPS, the shift field directly encodes the shift
+ * amount, meaning that the supported shift values are in
+ * the range 0 to 3 (instead of 1 to 4 in MIPSR6). */
+ gen_lsa(ctx, OPC_LSA, rd, rs, rt,
+ extract32(ctx->opcode, 9, 2) - 1);
+ break;
case NM_POOL32AXF:
gen_pool32axf_nanomips_insn(env, ctx);
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 16/55] target/mips: Implement emulation of nanoMIPS ROTX instruction
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (14 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 15/55] target/mips: Add emulation of misc nanoMIPS instructions (pool p_lsx) Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 17/55] target/mips: Implement emulation of nanoMIPS EXTW instruction Aleksandar Markovic
` (38 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Matthew Fortune <matthew.fortune@mips.com>
Added a helper for ROTX based on the pseudocode from the
architecture spec. This instraction was not present in previous
MIPS instruction sets.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/helper.h | 2 ++
target/mips/op_helper.c | 94 +++++++++++++++++++++++++++++++++++++++++++++++++
target/mips/translate.c | 15 ++++++++
3 files changed, 111 insertions(+)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 5f49234..b2a780a 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -40,6 +40,8 @@ DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl)
#endif
+DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32)
+
#ifndef CONFIG_USER_ONLY
/* CP0 helpers */
DEF_HELPER_1(mfc0_mvpcontrol, tl, env)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 0b2663b..b3eef9f 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -249,6 +249,100 @@ target_ulong helper_bitswap(target_ulong rt)
return (int32_t)bitswap(rt);
}
+target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx,
+ uint32_t stripe)
+{
+ int i;
+ uint64_t tmp0 = ((uint64_t)rs) << 32 | ((uint64_t)rs & 0xffffffff);
+ uint64_t tmp1 = tmp0;
+ for (i = 0; i <= 46; i++) {
+ int s;
+ if (i & 0x8) {
+ s = shift;
+ } else {
+ s = shiftx;
+ }
+
+ if (stripe != 0 && !(i & 0x4)) {
+ s = ~s;
+ }
+ if (s & 0x10) {
+ if (tmp0 & (1LL << (i + 16))) {
+ tmp1 |= 1LL << i;
+ } else {
+ tmp1 &= ~(1LL << i);
+ }
+ }
+ }
+
+ uint64_t tmp2 = tmp1;
+ for (i = 0; i <= 38; i++) {
+ int s;
+ if (i & 0x4) {
+ s = shift;
+ } else {
+ s = shiftx;
+ }
+
+ if (s & 0x8) {
+ if (tmp1 & (1LL << (i + 8))) {
+ tmp2 |= 1LL << i;
+ } else {
+ tmp2 &= ~(1LL << i);
+ }
+ }
+ }
+
+ uint64_t tmp3 = tmp2;
+ for (i = 0; i <= 34; i++) {
+ int s;
+ if (i & 0x2) {
+ s = shift;
+ } else {
+ s = shiftx;
+ }
+ if (s & 0x4) {
+ if (tmp2 & (1LL << (i + 4))) {
+ tmp3 |= 1LL << i;
+ } else {
+ tmp3 &= ~(1LL << i);
+ }
+ }
+ }
+
+ uint64_t tmp4 = tmp3;
+ for (i = 0; i <= 32; i++) {
+ int s;
+ if (i & 0x1) {
+ s = shift;
+ } else {
+ s = shiftx;
+ }
+ if (s & 0x2) {
+ if (tmp3 & (1LL << (i + 2))) {
+ tmp4 |= 1LL << i;
+ } else {
+ tmp4 &= ~(1LL << i);
+ }
+ }
+ }
+
+ uint64_t tmp5 = tmp4;
+ for (i = 0; i <= 31; i++) {
+ int s;
+ s = shift;
+ if (s & 0x1) {
+ if (tmp4 & (1LL << (i + 1))) {
+ tmp5 |= 1LL << i;
+ } else {
+ tmp5 &= ~(1LL << i);
+ }
+ }
+ }
+
+ return (int64_t)(int32_t)(uint32_t)tmp5;
+}
+
#ifndef CONFIG_USER_ONLY
static inline hwaddr do_translate_address(CPUMIPSState *env,
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 1aafb74..1d2bc02 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -17581,6 +17581,21 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case NM_P_ROTX:
+ if (rt != 0) {
+ TCGv t0 = tcg_temp_new();
+ TCGv_i32 shift = tcg_const_i32(extract32(ctx->opcode, 0, 5));
+ TCGv_i32 shiftx = tcg_const_i32(extract32(ctx->opcode, 7, 4)
+ << 1);
+ TCGv_i32 stripe = tcg_const_i32((ctx->opcode >> 6) & 1);
+
+ gen_load_gpr(t0, rs);
+ gen_helper_rotx(cpu_gpr[rt], t0, shift, shiftx, stripe);
+ tcg_temp_free(t0);
+
+ tcg_temp_free_i32(shift);
+ tcg_temp_free_i32(shiftx);
+ tcg_temp_free_i32(stripe);
+ }
break;
case NM_P_INS:
switch (((ctx->opcode >> 10) & 2) | ((ctx->opcode >> 5) & 1)) {
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 17/55] target/mips: Implement emulation of nanoMIPS EXTW instruction
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (15 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 16/55] target/mips: Implement emulation of nanoMIPS ROTX instruction Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 18/55] target/mips: Add emulation of nanoMIPS 32-bit load and store instructions Aleksandar Markovic
` (37 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: James Hogan <james.hogan@mips.com>
Implement emulation of nanoMIPS EXTW instruction. EXTW instruction
is similar to the MIPS r6 ALIGN instruction, except that it counts
the other way and in bits instead of bytes. We therefore generalise
gen_align() function into a new gen_align_bits() function (which
counts in bits instead of bytes and optimises when bits = size of
the word), and implement gen_align() and a new gen_ext() based on
that. Since we need to know the word size to check for when the
number of bits == the word size, the opc argument is replaced with
a wordsz argument (either 32 or 64).
Signed-off-by: James Hogan <james.hogan@mips.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/translate.c | 53 +++++++++++++++++++++++++++++++++----------------
1 file changed, 36 insertions(+), 17 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 1d2bc02..0977fab 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4723,8 +4723,8 @@ static void gen_lsa(DisasContext *ctx, int opc, int rd, int rs, int rt,
return;
}
-static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt,
- int bp)
+static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs,
+ int rt, int bits)
{
TCGv t0;
if (rd == 0) {
@@ -4732,35 +4732,40 @@ static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt,
return;
}
t0 = tcg_temp_new();
- gen_load_gpr(t0, rt);
- if (bp == 0) {
- switch (opc) {
- case OPC_ALIGN:
+ if (bits == 0 || bits == wordsz) {
+ if (bits == 0) {
+ gen_load_gpr(t0, rt);
+ } else {
+ gen_load_gpr(t0, rs);
+ }
+ switch (wordsz) {
+ case 32:
tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
break;
#if defined(TARGET_MIPS64)
- case OPC_DALIGN:
+ case 64:
tcg_gen_mov_tl(cpu_gpr[rd], t0);
break;
#endif
}
} else {
TCGv t1 = tcg_temp_new();
+ gen_load_gpr(t0, rt);
gen_load_gpr(t1, rs);
- switch (opc) {
- case OPC_ALIGN:
+ switch (wordsz) {
+ case 32:
{
TCGv_i64 t2 = tcg_temp_new_i64();
tcg_gen_concat_tl_i64(t2, t1, t0);
- tcg_gen_shri_i64(t2, t2, 8 * (4 - bp));
+ tcg_gen_shri_i64(t2, t2, 32 - bits);
gen_move_low32(cpu_gpr[rd], t2);
tcg_temp_free_i64(t2);
}
break;
#if defined(TARGET_MIPS64)
- case OPC_DALIGN:
- tcg_gen_shli_tl(t0, t0, 8 * bp);
- tcg_gen_shri_tl(t1, t1, 8 * (8 - bp));
+ case 64:
+ tcg_gen_shli_tl(t0, t0, bits);
+ tcg_gen_shri_tl(t1, t1, 64 - bits);
tcg_gen_or_tl(cpu_gpr[rd], t1, t0);
break;
#endif
@@ -4771,6 +4776,18 @@ static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt,
tcg_temp_free(t0);
}
+static void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt,
+ int bp)
+{
+ gen_align_bits(ctx, wordsz, rd, rs, rt, bp * 8);
+}
+
+static void gen_ext(DisasContext *ctx, int wordsz, int rd, int rs, int rt,
+ int shift)
+{
+ gen_align_bits(ctx, wordsz, rd, rs, rt, wordsz - shift);
+}
+
static void gen_bitswap(DisasContext *ctx, int opc, int rd, int rt)
{
TCGv t0;
@@ -14233,8 +14250,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case ALIGN:
check_insn(ctx, ISA_MIPS32R6);
- gen_align(ctx, OPC_ALIGN, rd, rs, rt,
- extract32(ctx->opcode, 9, 2));
+ gen_align(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 9, 2));
break;
case EXT:
gen_bitops(ctx, OPC_EXT, rt, rs, rr, rd);
@@ -17364,6 +17380,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_lsa(ctx, OPC_LSA, rd, rs, rt,
extract32(ctx->opcode, 9, 2) - 1);
break;
+ case NM_EXTW:
+ gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5));
+ break;
case NM_POOL32AXF:
gen_pool32axf_nanomips_insn(env, ctx);
break;
@@ -20264,7 +20283,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
switch (op2) {
case OPC_ALIGN:
case OPC_ALIGN_END:
- gen_align(ctx, OPC_ALIGN, rd, rs, rt, sa & 3);
+ gen_align(ctx, 32, rd, rs, rt, sa & 3);
break;
case OPC_BITSWAP:
gen_bitswap(ctx, op2, rd, rt);
@@ -20290,7 +20309,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
switch (op2) {
case OPC_DALIGN:
case OPC_DALIGN_END:
- gen_align(ctx, OPC_DALIGN, rd, rs, rt, sa & 7);
+ gen_align(ctx, 64, rd, rs, rt, sa & 7);
break;
case OPC_DBITSWAP:
gen_bitswap(ctx, op2, rd, rt);
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 18/55] target/mips: Add emulation of nanoMIPS 32-bit load and store instructions
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (16 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 17/55] target/mips: Implement emulation of nanoMIPS EXTW instruction Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 19/55] target/mips: Add emulation of nanoMIPS branch instructions Aleksandar Markovic
` (36 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Yongbok Kim <yongbok.kim@mips.com>
Add emulation of various nanoMIPS load and store instructions.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 271 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 271 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 0977fab..b87a29e 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -17671,10 +17671,281 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case NM_P_GP_BH:
+ {
+ uint32_t u = extract32(ctx->opcode, 0, 18);
+ switch ((ctx->opcode >> 18) & 0x7) {
+ case NM_LBGP:
+ gen_ld(ctx, OPC_LB, rt, 28, u);
+ break;
+ case NM_SBGP:
+ gen_st(ctx, OPC_SB, rt, 28, u);
+ break;
+ case NM_LBUGP:
+ gen_ld(ctx, OPC_LBU, rt, 28, u);
+ break;
+ case NM_ADDIUGP_B:
+ gen_arith_imm(ctx, OPC_ADDIU, rt, 28, u);
+ break;
+ case NM_P_GP_LH:
+ u &= ~1;
+ switch (ctx->opcode & 1) {
+ case NM_LHGP:
+ gen_ld(ctx, OPC_LH, rt, 28, u);
+ break;
+ case NM_LHUGP:
+ gen_ld(ctx, OPC_LHU, rt, 28, u);
+ break;
+ }
+ break;
+ case NM_P_GP_SH:
+ u &= ~1;
+ switch (ctx->opcode & 1) {
+ case NM_SHGP:
+ gen_st(ctx, OPC_SH, rt, 28, u);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ case NM_P_GP_CP1:
+ u &= ~0x3;
+ switch ((ctx->opcode & 0x3)) {
+ case NM_LWC1GP:
+ gen_cop1_ldst(ctx, OPC_LWC1, rt, 28, u);
+ break;
+ case NM_LDC1GP:
+ gen_cop1_ldst(ctx, OPC_LDC1, rt, 28, u);
+ break;
+ case NM_SWC1GP:
+ gen_cop1_ldst(ctx, OPC_SWC1, rt, 28, u);
+ break;
+ case NM_SDC1GP:
+ gen_cop1_ldst(ctx, OPC_SDC1, rt, 28, u);
+ break;
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ }
break;
case NM_P_LS_U12:
+ {
+ uint32_t u = extract32(ctx->opcode, 0, 12);
+ switch ((ctx->opcode >> 12) & 0x0f) {
+ case NM_P_PREFU12:
+ if (rt == 31) {
+ /* SYNCI */
+ /* Break the TB to be able to sync copied instructions
+ immediately */
+ ctx->base.is_jmp = DISAS_STOP;
+ } else {
+ /* PREF */
+ /* Treat as NOP. */
+ }
+ break;
+ case NM_LB:
+ gen_ld(ctx, OPC_LB, rt, rs, u);
+ break;
+ case NM_LH:
+ gen_ld(ctx, OPC_LH, rt, rs, u);
+ break;
+ case NM_LW:
+ gen_ld(ctx, OPC_LW, rt, rs, u);
+ break;
+ case NM_LBU:
+ gen_ld(ctx, OPC_LBU, rt, rs, u);
+ break;
+ case NM_LHU:
+ gen_ld(ctx, OPC_LHU, rt, rs, u);
+ break;
+ case NM_SB:
+ gen_st(ctx, OPC_SB, rt, rs, u);
+ break;
+ case NM_SH:
+ gen_st(ctx, OPC_SH, rt, rs, u);
+ break;
+ case NM_SW:
+ gen_st(ctx, OPC_SW, rt, rs, u);
+ break;
+ case NM_LWC1:
+ gen_cop1_ldst(ctx, OPC_LWC1, rt, rs, u);
+ break;
+ case NM_LDC1:
+ gen_cop1_ldst(ctx, OPC_LDC1, rt, rs, u);
+ break;
+ case NM_SWC1:
+ gen_cop1_ldst(ctx, OPC_SWC1, rt, rs, u);
+ break;
+ case NM_SDC1:
+ gen_cop1_ldst(ctx, OPC_SDC1, rt, rs, u);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ }
break;
case NM_P_LS_S9:
+ {
+ int32_t s = (sextract32(ctx->opcode, 15, 1) << 8) |
+ extract32(ctx->opcode, 0, 8);
+ switch ((ctx->opcode >> 8) & 0x07) {
+ case NM_P_LS_S0:
+ switch ((ctx->opcode >> 11) & 0x0f) {
+ case NM_LBS9:
+ gen_ld(ctx, OPC_LB, rt, rs, s);
+ break;
+ case NM_LHS9:
+ gen_ld(ctx, OPC_LH, rt, rs, s);
+ break;
+ case NM_LWS9:
+ gen_ld(ctx, OPC_LW, rt, rs, s);
+ break;
+ case NM_LBUS9:
+ gen_ld(ctx, OPC_LBU, rt, rs, s);
+ break;
+ case NM_LHUS9:
+ gen_ld(ctx, OPC_LHU, rt, rs, s);
+ break;
+ case NM_SBS9:
+ gen_st(ctx, OPC_SB, rt, rs, s);
+ break;
+ case NM_SHS9:
+ gen_st(ctx, OPC_SH, rt, rs, s);
+ break;
+ case NM_SWS9:
+ gen_st(ctx, OPC_SW, rt, rs, s);
+ break;
+ case NM_LWC1S9:
+ gen_cop1_ldst(ctx, OPC_LWC1, rt, rs, s);
+ break;
+ case NM_LDC1S9:
+ gen_cop1_ldst(ctx, OPC_LDC1, rt, rs, s);
+ break;
+ case NM_SWC1S9:
+ gen_cop1_ldst(ctx, OPC_SWC1, rt, rs, s);
+ break;
+ case NM_SDC1S9:
+ gen_cop1_ldst(ctx, OPC_SDC1, rt, rs, s);
+ break;
+ case NM_P_PREFS9:
+ if (rt == 31) {
+ /* SYNCI */
+ /* Break the TB to be able to sync copied instructions
+ immediately */
+ ctx->base.is_jmp = DISAS_STOP;
+ } else {
+ /* PREF */
+ /* Treat as NOP. */
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ case NM_P_LS_S1:
+ switch ((ctx->opcode >> 11) & 0x0f) {
+ case NM_UALH:
+ case NM_UASH:
+ {
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+
+ gen_base_offset_addr(ctx, t0, rs, s);
+
+ switch ((ctx->opcode >> 11) & 0x0f) {
+ case NM_UALH:
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW |
+ MO_UNALN);
+ gen_store_gpr(t0, rt);
+ break;
+ case NM_UASH:
+ gen_load_gpr(t1, rt);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW |
+ MO_UNALN);
+ break;
+ }
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+ break;
+ case NM_P_LL:
+ switch (ctx->opcode & 0x03) {
+ case NM_LL:
+ gen_ld(ctx, OPC_LL, rt, rs, s);
+ break;
+ case NM_LLWP:
+ break;
+ }
+ break;
+ case NM_P_SC:
+ switch (ctx->opcode & 0x03) {
+ case NM_SC:
+ gen_st_cond(ctx, OPC_SC, rt, rs, s);
+ break;
+ case NM_SCWP:
+ break;
+ }
+ break;
+ case NM_CACHE:
+ check_cp0_enabled(ctx);
+ if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
+ gen_cache_operation(ctx, rt, rs, s);
+ }
+ break;
+ }
+ break;
+ case NM_P_LS_WM:
+ case NM_P_LS_UAWM:
+ {
+ int32_t offset = sextract32(ctx->opcode, 15, 1) << 8 |
+ extract32(ctx->opcode, 0, 8);
+ int count = extract32(ctx->opcode, 12, 3);
+ int counter = 0;
+ TCGv va = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGMemOp memop = ((ctx->opcode >> 8) & 0x07) == NM_P_LS_UAWM ?
+ MO_UNALN : 0;
+
+ count = (count == 0) ? 8 : count;
+ while (counter != count) {
+ int this_rt = ((rt + counter) & 0x1f) | (rt & 0x10);
+ int32_t this_offset = offset + (counter << 2);
+
+ gen_base_offset_addr(ctx, va, rs, this_offset);
+
+ switch (extract32(ctx->opcode, 11, 1)) {
+ case NM_LWM:
+ tcg_gen_qemu_ld_tl(t1, va, ctx->mem_idx,
+ memop | MO_TESL);
+ gen_store_gpr(t1, this_rt);
+ if ((this_rt == rs) &&
+ (counter != (count - 1))) {
+ /* UNPREDICTABLE */
+ }
+ break;
+ case NM_SWM:
+ this_rt = (rt == 0) ? 0 : this_rt;
+ gen_load_gpr(t1, this_rt);
+ tcg_gen_qemu_st_tl(t1, va, ctx->mem_idx,
+ memop | MO_TEUL);
+ break;
+ }
+ counter++;
+ }
+ tcg_temp_free(va);
+ tcg_temp_free(t1);
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ }
break;
case NM_MOVE_BALC:
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 19/55] target/mips: Add emulation of nanoMIPS branch instructions
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (17 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 18/55] target/mips: Add emulation of nanoMIPS 32-bit load and store instructions Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 20/55] target/mips: Implement MT ASE support for nanoMIPS Aleksandar Markovic
` (35 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Yongbok Kim <yongbok.kim@mips.com>
Add emulation of various flavors of nanoMIPS branch instructions.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 277 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 277 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index b87a29e..9baacff 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16873,6 +16873,168 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
}
}
+/* Immediate Value Compact Branches */
+static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
+ int rt, int32_t imm, int32_t offset)
+{
+ int bcond_compute = 0;
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+
+ if (ctx->hflags & MIPS_HFLAG_BMASK) {
+#ifdef MIPS_DEBUG_DISAS
+ LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
+ "\n", ctx->base.pc_next);
+#endif
+ generate_exception_end(ctx, EXCP_RI);
+ goto out;
+ }
+
+ gen_load_gpr(t0, rt);
+ tcg_gen_movi_tl(t1, imm);
+ ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
+
+ /* Load needed operands and calculate btarget */
+ switch (opc) {
+ case NM_BEQIC:
+ if (rt == 0 && imm == 0) {
+ /* Unconditional branch */
+ } else if (rt == 0 && imm != 0) {
+ /* Treat as NOP */
+ goto out;
+ } else {
+ bcond_compute = 1;
+ }
+ break;
+ case NM_BBEQZC:
+ case NM_BBNEZC:
+ if (imm >= 32 && !(ctx->hflags & MIPS_HFLAG_64)) {
+ generate_exception_end(ctx, EXCP_RI);
+ goto out;
+ } else if (rt == 0 && opc == NM_BBEQZC) {
+ /* Unconditional branch */
+ } else if (rt == 0 && opc == NM_BBNEZC) {
+ /* Treat as NOP */
+ goto out;
+ } else {
+ tcg_gen_shri_tl(t0, t0, imm);
+ tcg_gen_andi_tl(t0, t0, 1);
+ tcg_gen_movi_tl(t1, 0);
+ bcond_compute = 1;
+ }
+ break;
+ case NM_BNEIC:
+ if (rt == 0 && imm == 0) {
+ /* Treat as NOP */
+ goto out;
+ } else if (rt == 0 && imm != 0) {
+ /* Unconditional branch */
+ } else {
+ bcond_compute = 1;
+ }
+ break;
+ case NM_BGEIC:
+ if (rt == 0 && imm == 0) {
+ /* Unconditional branch */
+ } else {
+ bcond_compute = 1;
+ }
+ break;
+ case NM_BLTIC:
+ bcond_compute = 1;
+ break;
+ case NM_BGEIUC:
+ if (rt == 0 && imm == 0) {
+ /* Unconditional branch */
+ } else {
+ bcond_compute = 1;
+ }
+ break;
+ case NM_BLTIUC:
+ bcond_compute = 1;
+ break;
+ default:
+ MIPS_INVAL("Immediate Value Compact branch");
+ generate_exception_end(ctx, EXCP_RI);
+ goto out;
+ }
+
+ if (bcond_compute == 0) {
+ /* Uncoditional compact branch */
+ ctx->hflags |= MIPS_HFLAG_B;
+ /* Generating branch here as compact branches don't have delay slot */
+ gen_branch(ctx, 4);
+ } else {
+ /* Conditional compact branch */
+ TCGLabel *fs = gen_new_label();
+ save_cpu_state(ctx, 0);
+
+ switch (opc) {
+ case NM_BEQIC:
+ tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_EQ), t0, t1, fs);
+ break;
+ case NM_BBEQZC:
+ tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_EQ), t0, t1, fs);
+ break;
+ case NM_BNEIC:
+ tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_NE), t0, t1, fs);
+ break;
+ case NM_BBNEZC:
+ tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_NE), t0, t1, fs);
+ break;
+ case NM_BGEIC:
+ tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GE), t0, t1, fs);
+ break;
+ case NM_BLTIC:
+ tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LT), t0, t1, fs);
+ break;
+ case NM_BGEIUC:
+ tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GEU), t0, t1, fs);
+ break;
+ case NM_BLTIUC:
+ tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LTU), t0, t1, fs);
+ break;
+ }
+
+ /* Generating branch here as compact branches don't have delay slot */
+ gen_goto_tb(ctx, 1, ctx->btarget);
+ gen_set_label(fs);
+
+ ctx->hflags |= MIPS_HFLAG_FBNSLOT;
+ }
+
+out:
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
+/* P.BALRSC type nanoMIPS R6 branches: BALRSC and BRSC */
+static void gen_compute_nanomips_pbalrsc_branch(DisasContext *ctx, int rs,
+ int rt)
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+
+ /* load rs */
+ gen_load_gpr(t0, rs);
+
+ /* link */
+ if (rt != 0) {
+ tcg_gen_movi_tl(cpu_gpr[rt], ctx->base.pc_next + 4);
+ }
+
+ /* calculate btarget */
+ tcg_gen_shli_tl(t0, t0, 1);
+ tcg_gen_movi_tl(t1, ctx->base.pc_next + 4);
+ gen_op_addr_add(ctx, btarget, t1, t0);
+
+ ctx->hflags |= MIPS_HFLAG_BR;
+ /* Generating branch here as compact branches don't have delay slot */
+ gen_branch(ctx, 4);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
{
@@ -17948,16 +18110,131 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case NM_MOVE_BALC:
+ {
+ TCGv t0 = tcg_temp_new();
+ int32_t s = sextract32(ctx->opcode, 0, 1) << 21 |
+ extract32(ctx->opcode, 1, 20) << 1;
+ rd = ((ctx->opcode >> 24) & 1) == 0 ? 4 : 5;
+ rt = decode_gpr_gpr4_zero(extract32(ctx->opcode, 25, 1) << 3 |
+ extract32(ctx->opcode, 21, 3));
+ gen_load_gpr(t0, rt);
+ tcg_gen_mov_tl(cpu_gpr[rd], t0);
+ gen_compute_branch(ctx, OPC_BGEZAL, 4, 0, 0, s, 0);
+ tcg_temp_free(t0);
+ }
break;
case NM_P_BAL:
+ {
+ int32_t s = sextract32(ctx->opcode, 0, 1) << 25 |
+ extract32(ctx->opcode, 1, 24) << 1;
+
+ if (((ctx->opcode >> 25) & 1) == 0) {
+ /* BC */
+ gen_compute_branch(ctx, OPC_BEQ, 4, 0, 0, s, 0);
+ } else {
+ /* BALC */
+ gen_compute_branch(ctx, OPC_BGEZAL, 4, 0, 0, s, 0);
+ }
+ }
break;
case NM_P_J:
+ switch ((ctx->opcode >> 12) & 0x0f) {
+ case NM_JALRC:
+ case NM_JALRC_HB:
+ gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 0);
+ break;
+ case NM_P_BALRSC:
+ gen_compute_nanomips_pbalrsc_branch(ctx, rs, rt);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
break;
case NM_P_BR1:
+ {
+ int32_t s = sextract32(ctx->opcode, 0, 1) << 14 |
+ extract32(ctx->opcode, 1, 13) << 1;
+ switch ((ctx->opcode >> 14) & 0x03) {
+ case NM_BEQC:
+ gen_compute_branch(ctx, OPC_BEQ, 4, rs, rt, s, 0);
+ break;
+ case NM_P_BR3A:
+ {
+ int32_t s = sextract32(ctx->opcode, 0, 1) << 14 |
+ extract32(ctx->opcode, 1, 13) << 1;
+ check_cp1_enabled(ctx);
+ switch ((ctx->opcode >> 16) & 0x1f) {
+ case NM_BC1EQZC:
+ gen_compute_branch1_r6(ctx, OPC_BC1EQZ, rt, s, 0);
+ break;
+ case NM_BC1NEZC:
+ gen_compute_branch1_r6(ctx, OPC_BC1NEZ, rt, s, 0);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ }
+ break;
+ case NM_BGEC:
+ if (rs == rt) {
+ gen_compute_compact_branch(ctx, OPC_BC, rs, rt, s);
+ } else {
+ gen_compute_compact_branch(ctx, OPC_BGEC, rs, rt, s);
+ }
+ break;
+ case NM_BGEUC:
+ if (rs == rt || rt == 0) {
+ gen_compute_compact_branch(ctx, OPC_BC, 0, 0, s);
+ } else if (rs == 0) {
+ gen_compute_compact_branch(ctx, OPC_BEQZC, rt, 0, s);
+ } else {
+ gen_compute_compact_branch(ctx, OPC_BGEUC, rs, rt, s);
+ }
+ break;
+ }
+ }
break;
case NM_P_BR2:
+ {
+ int32_t s = sextract32(ctx->opcode, 0, 1) << 14 |
+ extract32(ctx->opcode, 1, 13) << 1;
+ switch ((ctx->opcode >> 14) & 0x03) {
+ case NM_BNEC:
+ gen_compute_branch(ctx, OPC_BNE, 4, rs, rt, s, 0);
+ break;
+ case NM_BLTC:
+ if (rs != 0 && rt != 0 && rs == rt) {
+ /* NOP */
+ ctx->hflags |= MIPS_HFLAG_FBNSLOT;
+ } else {
+ gen_compute_compact_branch(ctx, OPC_BLTC, rs, rt, s);
+ }
+ break;
+ case NM_BLTUC:
+ if (rs == 0 || rs == rt) {
+ /* NOP */
+ ctx->hflags |= MIPS_HFLAG_FBNSLOT;
+ } else {
+ gen_compute_compact_branch(ctx, OPC_BLTUC, rs, rt, s);
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ }
break;
case NM_P_BRI:
+ {
+ int32_t s = sextract32(ctx->opcode, 0, 1) << 11 |
+ extract32(ctx->opcode, 1, 10) << 1;
+ uint32_t u = extract32(ctx->opcode, 11, 7);
+
+ gen_compute_imm_branch(ctx, extract32(ctx->opcode, 18, 3),
+ rt, u, s);
+ }
break;
default:
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 20/55] target/mips: Implement MT ASE support for nanoMIPS
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (18 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 19/55] target/mips: Add emulation of nanoMIPS branch instructions Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 21/55] target/mips: Add emulation of DSP ASE for nanoMIPS - part 1 Aleksandar Markovic
` (34 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Stefan Markovic <smarkovic@wavecomp.com>
Add emulation of MT ASE instructions for nanoMIPS.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/translate.c | 85 +++++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 83 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9baacff..c09416b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16606,7 +16606,7 @@ static void gen_pool16c_nanomips_insn(DisasContext *ctx)
}
}
-static void gen_pool32a0_nanomips_insn(DisasContext *ctx)
+static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
{
int rt = (ctx->opcode >> 21) & 0x1f;
int rs = (ctx->opcode >> 16) & 0x1f;
@@ -16779,6 +16779,87 @@ static void gen_pool32a0_nanomips_insn(DisasContext *ctx)
tcg_temp_free(t0);
}
break;
+ case NM_D_E_MT_VPE:
+ {
+ uint8_t sc = (ctx->opcode >> 10) & 1;
+ TCGv t0 = tcg_temp_new();
+
+ switch (sc) {
+ case 0:
+ if (rs == 1) {
+ /* DMT */
+ check_insn(ctx, ASE_MT);
+ gen_helper_dmt(t0);
+ gen_store_gpr(t0, rt);
+ } else if (rs == 0) {
+ /* DVPE */
+ check_insn(ctx, ASE_MT);
+ gen_helper_dvpe(t0, cpu_env);
+ gen_store_gpr(t0, rt);
+ } else {
+ generate_exception_end(ctx, EXCP_RI);
+ }
+ break;
+ case 1:
+ if (rs == 1) {
+ /* EMT */
+ check_insn(ctx, ASE_MT);
+ gen_helper_emt(t0);
+ gen_store_gpr(t0, rt);
+ } else if (rs == 0) {
+ /* EVPE */
+ check_insn(ctx, ASE_MT);
+ gen_helper_evpe(t0, cpu_env);
+ gen_store_gpr(t0, rt);
+ } else {
+ generate_exception_end(ctx, EXCP_RI);
+ }
+ break;
+ }
+
+ tcg_temp_free(t0);
+ }
+ break;
+ case NM_FORK:
+ check_insn(ctx, ASE_MT);
+ {
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+
+ gen_load_gpr(t0, rt);
+ gen_load_gpr(t1, rs);
+ gen_helper_fork(t0, t1);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+ break;
+ case NM_MFTR:
+ case NM_MFHTR:
+ check_insn(ctx, ASE_MT);
+ if (rd == 0) {
+ /* Treat as NOP. */
+ return;
+ }
+ gen_mftr(env, ctx, rs, rt, (ctx->opcode >> 10) & 1,
+ (ctx->opcode >> 11) & 0x1f, (ctx->opcode >> 3) & 1);
+ break;
+ case NM_MTTR:
+ case NM_MTHTR:
+ check_insn(ctx, ASE_MT);
+ gen_mttr(env, ctx, rs, rt, (ctx->opcode >> 10) & 1,
+ (ctx->opcode >> 11) & 0x1f, (ctx->opcode >> 3) & 1);
+ break;
+ case NM_YIELD:
+ check_insn(ctx, ASE_MT);
+ {
+ TCGv t0 = tcg_temp_new();
+
+ gen_load_gpr(t0, rs);
+ gen_helper_yield(t0, cpu_env, t0);
+ gen_store_gpr(t0, rt);
+ tcg_temp_free(t0);
+ }
+ break;
#endif
default:
generate_exception_end(ctx, EXCP_RI);
@@ -17528,7 +17609,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
case NM_POOL32A:
switch (ctx->opcode & 0x07) {
case NM_POOL32A0:
- gen_pool32a0_nanomips_insn(ctx);
+ gen_pool32a0_nanomips_insn(env, ctx);
break;
case NM_POOL32A7:
switch ((ctx->opcode >> 3) & 0x07) {
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 21/55] target/mips: Add emulation of DSP ASE for nanoMIPS - part 1
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (19 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 20/55] target/mips: Implement MT ASE support for nanoMIPS Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 22/55] target/mips: Add emulation of DSP ASE for nanoMIPS - part 2 Aleksandar Markovic
` (33 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Stefan Markovic <smarkovic@wavecomp.com>
Add emulation of DSP ASE instructions for nanoMIPS - part 1.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/translate.c | 525 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 525 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c09416b..e70359d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -17541,6 +17541,525 @@ static void gen_pool32f_nanomips_insn(DisasContext *ctx)
}
}
+static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
+ int rd, int rs, int rt)
+{
+ int ret = rd;
+
+ TCGv t1;
+ TCGv v1_t;
+ TCGv v2_t;
+
+ t1 = tcg_temp_new();
+ v1_t = tcg_temp_new();
+ v2_t = tcg_temp_new();
+
+ gen_load_gpr(v1_t, rs);
+ gen_load_gpr(v2_t, rt);
+
+ switch (opc) {
+ case OPC_CMP_EQ_PH:
+ check_dsp(ctx);
+ gen_helper_cmp_eq_ph(v1_t, v2_t, cpu_env);
+ break;
+ case OPC_CMP_LT_PH:
+ check_dsp(ctx);
+ gen_helper_cmp_lt_ph(v1_t, v2_t, cpu_env);
+ break;
+ case OPC_CMP_LE_PH:
+ check_dsp(ctx);
+ gen_helper_cmp_le_ph(v1_t, v2_t, cpu_env);
+ break;
+ case OPC_CMPU_EQ_QB:
+ check_dsp(ctx);
+ gen_helper_cmpu_eq_qb(v1_t, v2_t, cpu_env);
+ break;
+ case OPC_CMPU_LT_QB:
+ check_dsp(ctx);
+ gen_helper_cmpu_lt_qb(v1_t, v2_t, cpu_env);
+ break;
+ case OPC_CMPU_LE_QB:
+ check_dsp(ctx);
+ gen_helper_cmpu_le_qb(v1_t, v2_t, cpu_env);
+ break;
+ case OPC_CMPGU_EQ_QB:
+ check_dsp(ctx);
+ gen_helper_cmpgu_eq_qb(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ case OPC_CMPGU_LT_QB:
+ check_dsp(ctx);
+ gen_helper_cmpgu_lt_qb(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ case OPC_CMPGU_LE_QB:
+ check_dsp(ctx);
+ gen_helper_cmpgu_le_qb(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ case OPC_CMPGDU_EQ_QB:
+ check_dspr2(ctx);
+ gen_helper_cmpgu_eq_qb(t1, v1_t, v2_t);
+ tcg_gen_mov_tl(cpu_gpr[ret], t1);
+ tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
+ tcg_gen_shli_tl(t1, t1, 24);
+ tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1);
+ break;
+ case OPC_CMPGDU_LT_QB:
+ check_dspr2(ctx);
+ gen_helper_cmpgu_lt_qb(t1, v1_t, v2_t);
+ tcg_gen_mov_tl(cpu_gpr[ret], t1);
+ tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
+ tcg_gen_shli_tl(t1, t1, 24);
+ tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1);
+ break;
+ case OPC_CMPGDU_LE_QB:
+ check_dspr2(ctx);
+ gen_helper_cmpgu_le_qb(t1, v1_t, v2_t);
+ tcg_gen_mov_tl(cpu_gpr[ret], t1);
+ tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
+ tcg_gen_shli_tl(t1, t1, 24);
+ tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1);
+ break;
+ case OPC_PACKRL_PH:
+ check_dsp(ctx);
+ gen_helper_packrl_ph(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ case OPC_PICK_QB:
+ check_dsp(ctx);
+ gen_helper_pick_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ case OPC_PICK_PH:
+ check_dsp(ctx);
+ gen_helper_pick_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ case OPC_ADDQ_S_W:
+ check_dsp(ctx);
+ gen_helper_addq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ case OPC_SUBQ_S_W:
+ check_dsp(ctx);
+ gen_helper_subq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ case OPC_ADDSC:
+ check_dsp(ctx);
+ gen_helper_addsc(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ case OPC_ADDWC:
+ check_dsp(ctx);
+ gen_helper_addwc(cpu_gpr[rd], v1_t, v2_t, cpu_env);
+ break;
+ case OPC_ADDQ_S_PH:
+ switch ((ctx->opcode >> 10) & 0x1) {
+ case 0:
+ /* ADDQ_PH */
+ check_dsp(ctx);
+ gen_helper_addq_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ case 1:
+ /* ADDQ_S_PH */
+ check_dsp(ctx);
+ gen_helper_addq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ }
+ break;
+ case OPC_ADDQH_R_PH:
+ switch ((ctx->opcode >> 10) & 0x1) {
+ case 0:
+ /* ADDQH_PH */
+ gen_helper_addqh_ph(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ case 1:
+ /* ADDQH_R_PH */
+ gen_helper_addqh_r_ph(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ }
+ break;
+ case OPC_ADDQH_R_W:
+ switch ((ctx->opcode >> 10) & 0x1) {
+ case 0:
+ /* ADDQH_W */
+ gen_helper_addqh_w(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ case 1:
+ /* ADDQH_R_W */
+ gen_helper_addqh_r_w(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ }
+ break;
+ case OPC_ADDU_S_QB:
+ switch ((ctx->opcode >> 10) & 0x1) {
+ case 0:
+ /* ADDU_QB */
+ check_dsp(ctx);
+ gen_helper_addu_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ case 1:
+ /* ADDU_S_QB */
+ check_dsp(ctx);
+ gen_helper_addu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ }
+ break;
+ case OPC_ADDU_S_PH:
+ switch ((ctx->opcode >> 10) & 0x1) {
+ case 0:
+ /* ADDU_PH */
+ check_dspr2(ctx);
+ gen_helper_addu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ case 1:
+ /* ADDU_S_PH */
+ check_dspr2(ctx);
+ gen_helper_addu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ }
+ break;
+ case OPC_ADDUH_R_QB:
+ switch ((ctx->opcode >> 10) & 0x1) {
+ case 0:
+ /* ADDUH_QB */
+ gen_helper_adduh_qb(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ case 1:
+ /* ADDUH_R_QB */
+ gen_helper_adduh_r_qb(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ }
+ break;
+ case OPC_SHRAV_R_PH:
+ switch ((ctx->opcode >> 10) & 0x1) {
+ case 0:
+ /* SHRAV_PH */
+ check_dsp(ctx);
+ gen_helper_shra_ph(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ case 1:
+ /* SHRAV_R_PH */
+ check_dsp(ctx);
+ gen_helper_shra_r_ph(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ }
+ break;
+ case OPC_SHRAV_R_QB:
+ switch ((ctx->opcode >> 10) & 0x1) {
+ case 0:
+ /* SHRAV_QB */
+ check_dspr2(ctx);
+ gen_helper_shra_qb(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ case 1:
+ /* SHRAV_R_QB */
+ check_dspr2(ctx);
+ gen_helper_shra_r_qb(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ }
+ break;
+ case OPC_SUBQ_S_PH:
+ switch ((ctx->opcode >> 10) & 0x1) {
+ case 0:
+ /* SUBQ_PH */
+ check_dsp(ctx);
+ gen_helper_subq_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ case 1:
+ /* SUBQ_S_PH */
+ check_dsp(ctx);
+ gen_helper_subq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ }
+ break;
+ case OPC_SUBQH_R_PH:
+ switch ((ctx->opcode >> 10) & 0x1) {
+ case 0:
+ /* SUBQH_PH */
+ gen_helper_subqh_ph(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ case 1:
+ /* SUBQH_R_PH */
+ gen_helper_subqh_r_ph(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ }
+ break;
+ case OPC_SUBQH_R_W:
+ switch ((ctx->opcode >> 10) & 0x1) {
+ case 0:
+ /* SUBQH_W */
+ gen_helper_subqh_w(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ case 1:
+ /* SUBQH_R_W */
+ gen_helper_subqh_r_w(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ }
+ break;
+ case OPC_SUBU_S_QB:
+ switch ((ctx->opcode >> 10) & 0x1) {
+ case 0:
+ /* SUBU_QB */
+ check_dsp(ctx);
+ gen_helper_subu_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ case 1:
+ /* SUBU_S_QB */
+ check_dsp(ctx);
+ gen_helper_subu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ }
+ break;
+ case OPC_SUBU_S_PH:
+ switch ((ctx->opcode >> 10) & 0x1) {
+ case 0:
+ /* SUBU_PH */
+ check_dspr2(ctx);
+ gen_helper_subu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ case 1:
+ /* SUBU_S_PH */
+ check_dspr2(ctx);
+ gen_helper_subu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ }
+ break;
+ case OPC_SUBUH_R_QB:
+ switch ((ctx->opcode >> 10) & 0x1) {
+ case 0:
+ /* SUBUH_QB */
+ gen_helper_subuh_qb(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ case 1:
+ /* SUBUH_R_QB */
+ gen_helper_subuh_r_qb(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ }
+ break;
+ case OPC_SHLLV_S_PH:
+ switch ((ctx->opcode >> 10) & 0x1) {
+ case 0:
+ /* SHLLV_PH */
+ check_dsp(ctx);
+ gen_helper_shll_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ case 1:
+ /* SHLLV_S_PH */
+ check_dsp(ctx);
+ gen_helper_shll_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ }
+ break;
+ case OPC_PRECR_SRA_R_PH_W:
+ switch ((ctx->opcode >> 10) & 0x1) {
+ case 0:
+ /* PRECR_SRA_PH_W */
+ check_dspr2(ctx);
+ {
+ TCGv_i32 sa_t = tcg_const_i32(rd);
+ gen_helper_precr_sra_ph_w(cpu_gpr[rt], sa_t, v1_t,
+ cpu_gpr[rt]);
+ tcg_temp_free_i32(sa_t);
+ }
+ break;
+ case 1:
+ /* PRECR_SRA_R_PH_W */
+ check_dspr2(ctx);
+ {
+ TCGv_i32 sa_t = tcg_const_i32(rd);
+ gen_helper_precr_sra_r_ph_w(cpu_gpr[rt], sa_t, v1_t,
+ cpu_gpr[rt]);
+ tcg_temp_free_i32(sa_t);
+ }
+ break;
+ }
+ break;
+ case OPC_MULEU_S_PH_QBL:
+ check_dsp(ctx);
+ gen_helper_muleu_s_ph_qbl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ case OPC_MULEU_S_PH_QBR:
+ check_dsp(ctx);
+ gen_helper_muleu_s_ph_qbr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ case OPC_MULQ_RS_PH:
+ check_dsp(ctx);
+ gen_helper_mulq_rs_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ case OPC_MULQ_S_PH:
+ check_dspr2(ctx);
+ gen_helper_mulq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ case OPC_MULQ_RS_W:
+ gen_helper_mulq_rs_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ case OPC_MULQ_S_W:
+ gen_helper_mulq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ case OPC_APPEND:
+ {
+ TCGv t0;
+
+ t0 = tcg_temp_new();
+ gen_load_gpr(t0, rs);
+
+ if (rd != 0) {
+ tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], rd, 32 - rd);
+ }
+ tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
+ }
+ break;
+ case OPC_MODSUB:
+ check_dsp(ctx);
+ gen_helper_modsub(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ case OPC_SHRAV_R_W:
+ check_dsp(ctx);
+ gen_helper_shra_r_w(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ case OPC_SHRLV_PH:
+ check_dspr2(ctx);
+ gen_helper_shrl_ph(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ case OPC_SHRLV_QB:
+ check_dsp(ctx);
+ gen_helper_shrl_qb(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ case OPC_SHLLV_QB:
+ check_dsp(ctx);
+ gen_helper_shll_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ case OPC_SHLLV_S_W:
+ check_dsp(ctx);
+ gen_helper_shll_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ case OPC_SHILO:
+ {
+ TCGv t0;
+ TCGv t1;
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+
+ int16_t imm = (ctx->opcode >> 16) & 0x3F;
+
+ tcg_gen_movi_tl(t0, rd >> 3);
+ tcg_gen_movi_tl(t1, imm);
+
+ gen_helper_shilo(t0, t1, cpu_env);
+ }
+ break;
+ case OPC_MULEQ_S_W_PHL:
+ check_dsp(ctx);
+ gen_helper_muleq_s_w_phl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ case OPC_MULEQ_S_W_PHR:
+ check_dsp(ctx);
+ gen_helper_muleq_s_w_phr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ case OPC_MUL_S_PH:
+ switch ((ctx->opcode >> 10) & 0x1) {
+ case 0:
+ /* MUL_PH */
+ gen_helper_mul_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ case 1:
+ /* MUL_S_PH */
+ gen_helper_mul_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ }
+ break;
+ case OPC_PRECR_QB_PH:
+ check_dspr2(ctx);
+ gen_helper_precr_qb_ph(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ case OPC_PRECRQ_QB_PH:
+ check_dsp(ctx);
+ gen_helper_precrq_qb_ph(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ case OPC_PRECRQ_PH_W:
+ check_dsp(ctx);
+ gen_helper_precrq_ph_w(cpu_gpr[ret], v1_t, v2_t);
+ break;
+ case OPC_PRECRQ_RS_PH_W:
+ check_dsp(ctx);
+ gen_helper_precrq_rs_ph_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ case OPC_PRECRQU_S_QB_PH:
+ check_dsp(ctx);
+ gen_helper_precrqu_s_qb_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ break;
+ case OPC_SHRA_R_W:
+ {
+ TCGv t0;
+ t0 = tcg_temp_new();
+ tcg_gen_movi_tl(t0, rd);
+
+ check_dsp(ctx);
+ gen_helper_shra_r_w(cpu_gpr[rt], t0, v1_t);
+ }
+ break;
+ case OPC_SHRA_R_PH:
+ {
+ TCGv t0;
+ t0 = tcg_temp_new();
+ tcg_gen_movi_tl(t0, rd >> 1);
+
+ switch ((ctx->opcode >> 10) & 0x1) {
+ case 0:
+ /* SHRA_PH */
+ check_dsp(ctx);
+ gen_helper_shra_ph(cpu_gpr[rt], t0, v1_t);
+ break;
+ case 1:
+ /* SHRA_R_PH */
+ check_dsp(ctx);
+ gen_helper_shra_r_ph(cpu_gpr[rt], t0, v1_t);
+ break;
+ }
+ }
+ break;
+ case OPC_SHLL_S_PH:
+ {
+ TCGv t0;
+ t0 = tcg_temp_new();
+ tcg_gen_movi_tl(t0, rd >> 1);
+
+ switch ((ctx->opcode >> 10) & 0x3) {
+ case 0:
+ /* SHLL_PH */
+ check_dsp(ctx);
+ gen_helper_shll_ph(cpu_gpr[rt], t0, v1_t, cpu_env);
+ break;
+ case 2:
+ /* SHLL_S_PH */
+ check_dsp(ctx);
+ gen_helper_shll_s_ph(cpu_gpr[rt], t0, v1_t, cpu_env);
+ break;
+ }
+ }
+ break;
+ case OPC_SHLL_S_W:
+ {
+ TCGv t0;
+ t0 = tcg_temp_new();
+ tcg_gen_movi_tl(t0, rd);
+
+ check_dsp(ctx);
+ gen_helper_shll_s_w(cpu_gpr[rt], t0, v1_t, cpu_env);
+ break;
+ }
+ break;
+ case OPC_REPL_PH:
+ check_dsp(ctx);
+ {
+ int16_t imm;
+ imm = (ctx->opcode >> 11) & 0x03FF;
+ imm = (int16_t)(imm << 6) >> 6;
+ tcg_gen_movi_tl(cpu_gpr[rt], \
+ (target_long)((int32_t)imm << 16 | \
+ (uint16_t)imm));
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+}
+
static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
{
uint16_t insn;
@@ -17611,6 +18130,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
case NM_POOL32A0:
gen_pool32a0_nanomips_insn(env, ctx);
break;
+ case NM_POOL32A5:
+ {
+ int32_t op1 = (ctx->opcode >> 3) & 0x7F;
+ gen_pool32a5_nanomips_insn(ctx, op1, rd, rs, rt);
+ }
+ break;
case NM_POOL32A7:
switch ((ctx->opcode >> 3) & 0x07) {
case NM_P_LSX:
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 22/55] target/mips: Add emulation of DSP ASE for nanoMIPS - part 2
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (20 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 21/55] target/mips: Add emulation of DSP ASE for nanoMIPS - part 1 Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 23/55] target/mips: Add emulation of DSP ASE for nanoMIPS - part 3 Aleksandar Markovic
` (32 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Stefan Markovic <smarkovic@wavecomp.com>
Add emulation of DSP ASE instructions for nanoMIPS - part 2.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/translate.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index e70359d..cbdb613 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -18777,6 +18777,18 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
case NM_BC1NEZC:
gen_compute_branch1_r6(ctx, OPC_BC1NEZ, rt, s, 0);
break;
+ case NM_BPOSGE32C:
+ check_dsp(ctx);
+ {
+ int32_t imm = ctx->opcode;
+ imm >>= 1;
+ imm &= 0x1fff;
+ imm |= (ctx->opcode & 1) << 13;
+
+ gen_compute_branch(ctx, OPC_BPOSGE32, 4, -1, -2,
+ (int32_t)imm, 4);
+ }
+ break;
default:
generate_exception_end(ctx, EXCP_RI);
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 23/55] target/mips: Add emulation of DSP ASE for nanoMIPS - part 3
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (21 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 22/55] target/mips: Add emulation of DSP ASE for nanoMIPS - part 2 Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-25 15:04 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 24/55] target/mips: Add handling of branch delay slots for nanoMIPS Aleksandar Markovic
` (31 subsequent siblings)
54 siblings, 1 reply; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Stefan Markovic <smarkovic@wavecomp.com>
Add emulation of DSP ASE instructions for nanoMIPS - part 3.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/translate.c | 751 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 751 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index cbdb613..a8fbbe6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16867,13 +16867,758 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
}
}
+/* dsp */
+static void gen_pool32axf_1_5_nanomips_insn(DisasContext *ctx, uint32_t opc,
+ int ret, int v1, int v2)
+{
+ TCGv_i32 t0;
+ TCGv v0_t;
+ TCGv v1_t;
+
+ t0 = tcg_temp_new_i32();
+
+ v0_t = tcg_temp_new();
+ v1_t = tcg_temp_new();
+
+ tcg_gen_movi_i32(t0, v2 >> 3);
+
+ gen_load_gpr(v0_t, ret);
+ gen_load_gpr(v1_t, v1);
+
+ switch (opc) {
+ case NM_MAQ_S_W_PHR:
+ check_dsp(ctx);
+ gen_helper_maq_s_w_phr(t0, v1_t, v0_t, cpu_env);
+ break;
+ case NM_MAQ_S_W_PHL:
+ check_dsp(ctx);
+ gen_helper_maq_s_w_phl(t0, v1_t, v0_t, cpu_env);
+ break;
+ case NM_MAQ_SA_W_PHR:
+ check_dsp(ctx);
+ gen_helper_maq_sa_w_phr(t0, v1_t, v0_t, cpu_env);
+ break;
+ case NM_MAQ_SA_W_PHL:
+ check_dsp(ctx);
+ gen_helper_maq_sa_w_phl(t0, v1_t, v0_t, cpu_env);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+
+ tcg_temp_free_i32(t0);
+
+ tcg_temp_free(v0_t);
+ tcg_temp_free(v1_t);
+}
+
+
+static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
+ int ret, int v1, int v2)
+{
+ int16_t imm;
+
+ TCGv t0;
+ TCGv t1;
+ TCGv v0_t;
+ TCGv v1_t;
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+
+ v0_t = tcg_temp_new();
+ v1_t = tcg_temp_new();
+
+ gen_load_gpr(v0_t, ret);
+ gen_load_gpr(v1_t, v1);
+
+ switch (opc) {
+ case NM_POOL32AXF_1_0:
+ switch ((ctx->opcode >> 12) & 0x03) {
+ case NM_MFHI:
+ gen_HILO(ctx, OPC_MFHI, v2 >> 3, ret);
+ break;
+ case NM_MFLO:
+ gen_HILO(ctx, OPC_MFLO, v2 >> 3, ret);
+ break;
+ case NM_MTHI:
+ gen_HILO(ctx, OPC_MTHI, v2 >> 3, v1);
+ break;
+ case NM_MTLO:
+ gen_HILO(ctx, OPC_MTLO, v2 >> 3, v1);
+ break;
+ }
+ break;
+ case NM_POOL32AXF_1_1:
+ switch ((ctx->opcode >> 12) & 0x03) {
+ case NM_MTHLIP:
+ tcg_gen_movi_tl(t0, v2);
+ gen_helper_mthlip(t0, v1_t, cpu_env);
+ break;
+ case NM_SHILOV:
+ tcg_gen_movi_tl(t0, v2 >> 3);
+ gen_helper_shilo(t0, v1_t, cpu_env);
+ break;
+ }
+ break;
+ case NM_POOL32AXF_1_3:
+ imm = (ctx->opcode >> 14) & 0x07F;
+ switch ((ctx->opcode >> 12) & 0x03) {
+ case NM_RDDSP:
+ tcg_gen_movi_tl(t0, imm);
+ gen_helper_rddsp(cpu_gpr[ret], t0, cpu_env);
+ break;
+ case NM_WRDSP:
+ tcg_gen_movi_tl(t0, imm);
+ gen_helper_wrdsp(v0_t, t0, cpu_env);
+ break;
+ case NM_EXTP:
+ tcg_gen_movi_tl(t0, v2 >> 3);
+ tcg_gen_movi_tl(t1, v1);
+ gen_helper_extp(cpu_gpr[ret], t0, t1, cpu_env);
+ break;
+ case NM_EXTPDP:
+ tcg_gen_movi_tl(t0, v2 >> 3);
+ tcg_gen_movi_tl(t1, v1);
+ gen_helper_extpdp(cpu_gpr[ret], t0, t1, cpu_env);
+ break;
+ }
+ break;
+ case NM_POOL32AXF_1_4:
+ tcg_gen_movi_tl(t0, v2 >> 2);
+ switch ((ctx->opcode >> 12) & 0x01) {
+ case NM_SHLL_QB:
+ check_dsp(ctx);
+ gen_helper_shll_qb(cpu_gpr[ret], t0, v1_t, cpu_env);
+ break;
+ case NM_SHRL_QB:
+ check_dsp(ctx);
+ gen_helper_shrl_qb(cpu_gpr[ret], t0, v1_t);
+ break;
+ }
+ break;
+ case NM_POOL32AXF_1_5:
+ {
+ uint32_t opc = (ctx->opcode >> 12) & 0x03;
+ gen_pool32axf_1_5_nanomips_insn(ctx, opc, ret, v1, v2);
+ }
+ break;
+ case NM_POOL32AXF_1_7:
+ tcg_gen_movi_tl(t0, v2 >> 3);
+ tcg_gen_movi_tl(t1, v1);
+ switch ((ctx->opcode >> 12) & 0x03) {
+ case NM_EXTR_W:
+ gen_helper_extr_w(cpu_gpr[ret], t0, t1, cpu_env);
+ break;
+ case NM_EXTR_R_W:
+ gen_helper_extr_r_w(cpu_gpr[ret], t0, t1, cpu_env);
+ break;
+ case NM_EXTR_RS_W:
+ gen_helper_extr_rs_w(cpu_gpr[ret], t0, t1, cpu_env);
+ break;
+ case NM_EXTR_S_H:
+ gen_helper_extr_s_h(cpu_gpr[ret], t0, t1, cpu_env);
+ break;
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+
+ tcg_temp_free(v0_t);
+ tcg_temp_free(v1_t);
+}
+
+static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
+ int ret, int v1, int v2)
+{
+ TCGv_i32 t0;
+ TCGv v0_t;
+ TCGv v1_t;
+
+ t0 = tcg_temp_new_i32();
+
+ v0_t = tcg_temp_new();
+ v1_t = tcg_temp_new();
+
+ tcg_gen_movi_i32(t0, v2 >> 3);
+
+ gen_load_gpr(v0_t, ret);
+ gen_load_gpr(v1_t, v1);
+
+ switch (opc) {
+ case NM_POOL32AXF_2_0_7:
+ switch ((ctx->opcode >> 9) & 0x07) {
+ case NM_DPA_W_PH:
+ check_dspr2(ctx);
+ gen_helper_dpa_w_ph(t0, v1_t, v0_t, cpu_env);
+ break;
+ case NM_DPAQ_S_W_PH:
+ check_dsp(ctx);
+ gen_helper_dpaq_s_w_ph(t0, v1_t, v0_t, cpu_env);
+ break;
+ case NM_DPS_W_PH:
+ check_dspr2(ctx);
+ gen_helper_dps_w_ph(t0, v1_t, v0_t, cpu_env);
+ break;
+ case NM_DPSQ_S_W_PH:
+ check_dsp(ctx);
+ gen_helper_dpsq_s_w_ph(t0, v1_t, v0_t, cpu_env);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ case NM_POOL32AXF_2_8_15:
+ switch ((ctx->opcode >> 9) & 0x07) {
+ case NM_DPAX_W_PH:
+ check_dspr2(ctx);
+ gen_helper_dpax_w_ph(t0, v0_t, v1_t, cpu_env);
+ break;
+ case NM_DPAQ_SA_L_W:
+ check_dsp(ctx);
+ gen_helper_dpaq_sa_l_w(t0, v0_t, v1_t, cpu_env);
+ break;
+ case NM_DPSX_W_PH:
+ check_dspr2(ctx);
+ gen_helper_dpsx_w_ph(t0, v0_t, v1_t, cpu_env);
+ break;
+ case NM_DPSQ_SA_L_W:
+ check_dsp(ctx);
+ gen_helper_dpsq_sa_l_w(t0, v0_t, v1_t, cpu_env);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ case NM_POOL32AXF_2_16_23:
+ switch ((ctx->opcode >> 9) & 0x07) {
+ case NM_DPAU_H_QBL:
+ check_dsp(ctx);
+ gen_helper_dpau_h_qbl(t0, v0_t, v1_t, cpu_env);
+ break;
+ case NM_DPAQX_S_W_PH:
+ check_dspr2(ctx);
+ gen_helper_dpaqx_s_w_ph(t0, v0_t, v1_t, cpu_env);
+ break;
+ case NM_DPSU_H_QBL:
+ check_dsp(ctx);
+ gen_helper_dpsu_h_qbl(t0, v0_t, v1_t, cpu_env);
+ break;
+ case NM_DPSQX_S_W_PH:
+ check_dspr2(ctx);
+ gen_helper_dpsqx_s_w_ph(t0, v0_t, v1_t, cpu_env);
+ break;
+ case NM_MULSA_W_PH:
+ check_dspr2(ctx);
+ gen_helper_mulsa_w_ph(t0, v0_t, v1_t, cpu_env);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ case NM_POOL32AXF_2_24_31:
+ switch ((ctx->opcode >> 9) & 0x07) {
+ case NM_DPAU_H_QBR:
+ check_dsp(ctx);
+ gen_helper_dpau_h_qbr(t0, v1_t, v0_t, cpu_env);
+ break;
+ case NM_DPAQX_SA_W_PH:
+ check_dspr2(ctx);
+ gen_helper_dpaqx_sa_w_ph(t0, v1_t, v0_t, cpu_env);
+ break;
+ case NM_DPSU_H_QBR:
+ check_dsp(ctx);
+ gen_helper_dpsu_h_qbr(t0, v1_t, v0_t, cpu_env);
+ break;
+ case NM_DPSQX_SA_W_PH:
+ check_dspr2(ctx);
+ gen_helper_dpsqx_sa_w_ph(t0, v1_t, v0_t, cpu_env);
+ break;
+ case NM_MULSAQ_S_W_PH:
+ check_dsp(ctx);
+ gen_helper_mulsaq_s_w_ph(t0, v1_t, v0_t, cpu_env);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+
+ tcg_temp_free_i32(t0);
+
+ tcg_temp_free(v0_t);
+ tcg_temp_free(v1_t);
+}
+
+static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
+ int ret, int v1, int v2)
+{
+ TCGv t0;
+ TCGv t1;
+
+ TCGv v0_t;
+ TCGv v1_t;
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+
+ v0_t = tcg_temp_new();
+ v1_t = tcg_temp_new();
+
+ gen_load_gpr(v0_t, ret);
+ gen_load_gpr(v1_t, v1);
+
+ switch (opc) {
+ case NM_POOL32AXF_2_0_7:
+ switch ((ctx->opcode >> 9) & 0x07) {
+ case NM_DPA_W_PH:
+ case NM_DPAQ_S_W_PH:
+ case NM_DPS_W_PH:
+ case NM_DPSQ_S_W_PH:
+ gen_pool32axf_2_multiply(ctx, opc, ret, v1, v2);
+ break;
+ case NM_BALIGN:
+ gen_load_gpr(t0, v1);
+ v2 &= 3;
+ if (v2 != 0 && v2 != 2) {
+ tcg_gen_shli_tl(cpu_gpr[ret], cpu_gpr[ret], 8 * v2);
+ tcg_gen_ext32u_tl(t0, t0);
+ tcg_gen_shri_tl(t0, t0, 8 * (4 - v2));
+ tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
+ }
+ tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
+ break;
+ case NM_MADD:
+ {
+ int acc = (ctx->opcode >> 14) & 3;
+
+ gen_load_gpr(t0, ret);
+ gen_load_gpr(t1, v1);
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ TCGv_i64 t3 = tcg_temp_new_i64();
+
+ tcg_gen_ext_tl_i64(t2, t0);
+ tcg_gen_ext_tl_i64(t3, t1);
+ tcg_gen_mul_i64(t2, t2, t3);
+ tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
+ tcg_gen_add_i64(t2, t2, t3);
+ tcg_temp_free_i64(t3);
+ gen_move_low32(cpu_LO[acc], t2);
+ gen_move_high32(cpu_HI[acc], t2);
+ tcg_temp_free_i64(t2);
+ }
+ break;
+ case NM_MULT:
+ {
+ int acc = (ctx->opcode >> 14) & 3;
+
+ gen_load_gpr(t0, v1);
+ gen_load_gpr(t1, ret);
+
+ TCGv_i32 t2 = tcg_temp_new_i32();
+ TCGv_i32 t3 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(t2, t0);
+ tcg_gen_trunc_tl_i32(t3, t1);
+ tcg_gen_muls2_i32(t2, t3, t2, t3);
+ tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
+ tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t3);
+ }
+ break;
+ case NM_EXTRV_W:
+ gen_load_gpr(v1_t, v1);
+ tcg_gen_movi_tl(t0, v2 >> 3);
+ gen_helper_extr_w(cpu_gpr[ret], t0, v1_t, cpu_env);
+ break;
+ }
+ break;
+ case NM_POOL32AXF_2_8_15:
+ switch ((ctx->opcode >> 9) & 0x07) {
+ case NM_DPAX_W_PH:
+ case NM_DPAQ_SA_L_W:
+ case NM_DPSX_W_PH:
+ case NM_DPSQ_SA_L_W:
+ gen_pool32axf_2_multiply(ctx, opc, ret, v1, v2);
+ break;
+ case NM_MADDU:
+ {
+ int acc = (ctx->opcode >> 14) & 3;
+
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ TCGv_i64 t3 = tcg_temp_new_i64();
+
+ gen_load_gpr(t0, v1);
+ gen_load_gpr(t1, ret);
+
+ tcg_gen_ext32u_tl(t0, t0);
+ tcg_gen_ext32u_tl(t1, t1);
+ tcg_gen_extu_tl_i64(t2, t0);
+ tcg_gen_extu_tl_i64(t3, t1);
+ tcg_gen_mul_i64(t2, t2, t3);
+ tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
+ tcg_gen_add_i64(t2, t2, t3);
+ tcg_temp_free_i64(t3);
+ gen_move_low32(cpu_LO[acc], t2);
+ gen_move_high32(cpu_HI[acc], t2);
+ tcg_temp_free_i64(t2);
+ }
+ break;
+ case NM_MULTU:
+ {
+ int acc = (ctx->opcode >> 14) & 3;
+
+ TCGv_i32 t2 = tcg_temp_new_i32();
+ TCGv_i32 t3 = tcg_temp_new_i32();
+
+ gen_load_gpr(t0, v1);
+ gen_load_gpr(t1, ret);
+
+ tcg_gen_trunc_tl_i32(t2, t0);
+ tcg_gen_trunc_tl_i32(t3, t1);
+ tcg_gen_mulu2_i32(t2, t3, t2, t3);
+ tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
+ tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t3);
+ }
+ break;
+ case NM_EXTRV_R_W:
+ tcg_gen_movi_tl(t0, v2 >> 3);
+ gen_helper_extr_r_w(cpu_gpr[ret], t0, v1_t, cpu_env);
+ break;
+ }
+ break;
+ case NM_POOL32AXF_2_16_23:
+ switch ((ctx->opcode >> 9) & 0x07) {
+ case NM_DPAU_H_QBL:
+ case NM_DPAQX_S_W_PH:
+ case NM_DPSU_H_QBL:
+ case NM_DPSQX_S_W_PH:
+ case NM_MULSA_W_PH:
+ gen_pool32axf_2_multiply(ctx, opc, ret, v1, v2);
+ break;
+ case NM_EXTPV:
+ tcg_gen_movi_tl(t0, v2 >> 3);
+ gen_helper_extp(cpu_gpr[ret], t0, v1_t, cpu_env);
+ break;
+ case NM_MSUB:
+ {
+ int acc = (ctx->opcode >> 14) & 3;
+
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ TCGv_i64 t3 = tcg_temp_new_i64();
+
+ gen_load_gpr(t0, v1);
+ gen_load_gpr(t1, ret);
+
+ tcg_gen_ext_tl_i64(t2, t0);
+ tcg_gen_ext_tl_i64(t3, t1);
+ tcg_gen_mul_i64(t2, t2, t3);
+ tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
+ tcg_gen_sub_i64(t2, t3, t2);
+ tcg_temp_free_i64(t3);
+ gen_move_low32(cpu_LO[acc], t2);
+ gen_move_high32(cpu_HI[acc], t2);
+ tcg_temp_free_i64(t2);
+ }
+ break;
+ case NM_EXTRV_RS_W:
+ tcg_gen_movi_tl(t0, v2 >> 3);
+ gen_helper_extr_rs_w(cpu_gpr[ret], t0, v1_t, cpu_env);
+ break;
+ }
+ break;
+ case NM_POOL32AXF_2_24_31:
+ switch ((ctx->opcode >> 9) & 0x07) {
+ case NM_DPAU_H_QBR:
+ case NM_DPAQX_SA_W_PH:
+ case NM_DPSU_H_QBR:
+ case NM_DPSQX_SA_W_PH:
+ case NM_MULSAQ_S_W_PH:
+ gen_pool32axf_2_multiply(ctx, opc, ret, v1, v2);
+ break;
+ case NM_EXTPDPV:
+ tcg_gen_movi_tl(t0, v2 >> 3);
+ gen_helper_extpdp(cpu_gpr[ret], t0, v1_t, cpu_env);
+ break;
+ case NM_MSUBU:
+ {
+ int acc = (ctx->opcode >> 14) & 3;
+
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ TCGv_i64 t3 = tcg_temp_new_i64();
+
+ gen_load_gpr(t0, v1);
+ gen_load_gpr(t1, ret);
+
+ tcg_gen_ext32u_tl(t0, t0);
+ tcg_gen_ext32u_tl(t1, t1);
+ tcg_gen_extu_tl_i64(t2, t0);
+ tcg_gen_extu_tl_i64(t3, t1);
+ tcg_gen_mul_i64(t2, t2, t3);
+ tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
+ tcg_gen_sub_i64(t2, t3, t2);
+ tcg_temp_free_i64(t3);
+ gen_move_low32(cpu_LO[acc], t2);
+ gen_move_high32(cpu_HI[acc], t2);
+ tcg_temp_free_i64(t2);
+ }
+ break;
+ case NM_EXTRV_S_H:
+ tcg_gen_movi_tl(t0, v2 >> 3);
+ gen_helper_extr_s_h(cpu_gpr[ret], t0, v1_t, cpu_env);
+ break;
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+
+ tcg_temp_free(v0_t);
+ tcg_temp_free(v1_t);
+}
+
+static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc,
+ int ret, int v1, int v2)
+{
+ TCGv t0;
+ TCGv v0_t;
+ TCGv v1_t;
+
+ t0 = tcg_temp_new();
+
+ v0_t = tcg_temp_new();
+ v1_t = tcg_temp_new();
+
+ gen_load_gpr(v0_t, ret);
+ gen_load_gpr(v1_t, v1);
+
+ switch (opc) {
+ case NM_ABSQ_S_QB:
+ check_dspr2(ctx);
+ gen_helper_absq_s_qb(cpu_gpr[ret], v0_t, cpu_env);
+ break;
+ case NM_ABSQ_S_PH:
+ check_dsp(ctx);
+ gen_helper_absq_s_ph(cpu_gpr[ret], v1_t, cpu_env);
+ break;
+ case NM_ABSQ_S_W:
+ check_dsp(ctx);
+ gen_helper_absq_s_w(cpu_gpr[ret], v1_t, cpu_env);
+ break;
+ case NM_PRECEQ_W_PHL:
+ check_dsp(ctx);
+ tcg_gen_andi_tl(cpu_gpr[ret], v1_t, 0xFFFF0000);
+ tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
+ break;
+ case NM_PRECEQ_W_PHR:
+ check_dsp(ctx);
+ tcg_gen_andi_tl(cpu_gpr[ret], v1_t, 0x0000FFFF);
+ tcg_gen_shli_tl(cpu_gpr[ret], cpu_gpr[ret], 16);
+ tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
+ break;
+ case NM_PRECEQU_PH_QBL:
+ check_dsp(ctx);
+ gen_helper_precequ_ph_qbl(cpu_gpr[ret], v1_t);
+ break;
+ case NM_PRECEQU_PH_QBR:
+ check_dsp(ctx);
+ gen_helper_precequ_ph_qbr(cpu_gpr[ret], v1_t);
+ break;
+ case NM_PRECEQU_PH_QBLA:
+ check_dsp(ctx);
+ gen_helper_precequ_ph_qbla(cpu_gpr[ret], v1_t);
+ break;
+ case NM_PRECEQU_PH_QBRA:
+ check_dsp(ctx);
+ gen_helper_precequ_ph_qbra(cpu_gpr[ret], v1_t);
+ break;
+ case NM_PRECEU_PH_QBL:
+ check_dsp(ctx);
+ gen_helper_preceu_ph_qbl(cpu_gpr[ret], v1_t);
+ break;
+ case NM_PRECEU_PH_QBR:
+ check_dsp(ctx);
+ gen_helper_preceu_ph_qbr(cpu_gpr[ret], v1_t);
+ break;
+ case NM_PRECEU_PH_QBLA:
+ check_dsp(ctx);
+ gen_helper_preceu_ph_qbla(cpu_gpr[ret], v1_t);
+ break;
+ case NM_PRECEU_PH_QBRA:
+ check_dsp(ctx);
+ gen_helper_preceu_ph_qbra(cpu_gpr[ret], v1_t);
+ break;
+ case NM_REPLV_PH:
+ check_dsp(ctx);
+ tcg_gen_ext16u_tl(cpu_gpr[ret], v1_t);
+ tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
+ tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
+ tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
+ break;
+ case NM_REPLV_QB:
+ check_dsp(ctx);
+ {
+ TCGv val_t;
+
+ val_t = tcg_temp_new();
+ gen_load_gpr(val_t, v1);
+
+ tcg_gen_ext8u_tl(cpu_gpr[ret], val_t);
+ tcg_gen_shli_tl(t0, cpu_gpr[ret], 8);
+ tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
+ tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
+ tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
+ tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
+ }
+ break;
+ case NM_BITREV:
+ check_dsp(ctx);
+ gen_helper_bitrev(cpu_gpr[ret], v1_t);
+ break;
+ case NM_INSV:
+ check_dsp(ctx);
+ {
+ TCGv t0, t1;
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+
+ gen_load_gpr(t0, ret);
+ gen_load_gpr(t1, v1);
+
+ gen_helper_insv(cpu_gpr[ret], cpu_env, t1, t0);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+ break;
+ case NM_RADDU_W_QB:
+ check_dsp(ctx);
+ gen_helper_raddu_w_qb(cpu_gpr[ret], v1_t);
+ break;
+ case NM_BITSWAP:
+ gen_bitswap(ctx, OPC_BITSWAP, ret, v1);
+ break;
+ case NM_CLO:
+ gen_cl(ctx, OPC_CLO, ret, v1);
+ break;
+ case NM_CLZ:
+ gen_cl(ctx, OPC_CLZ, ret, v1);
+ break;
+ case NM_WSBH:
+ gen_bshfl(ctx, OPC_WSBH, ret, v1);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+
+ tcg_temp_free(t0);
+
+ tcg_temp_free(v0_t);
+ tcg_temp_free(v1_t);
+}
+
+static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc,
+ int ret, int v1, int v2)
+{
+ int16_t imm;
+
+ TCGv t0;
+ TCGv v1_t;
+
+ t0 = tcg_temp_new();
+ v1_t = tcg_temp_new();
+
+ gen_load_gpr(v1_t, v1);
+
+ switch (opc) {
+ case NM_SHRA_R_QB:
+ tcg_gen_movi_tl(t0, v2 >> 2);
+ switch ((ctx->opcode >> 12) & 0x01) {
+ case 0:
+ /* NM_SHRA_QB */
+ check_dspr2(ctx);
+ gen_helper_shra_qb(cpu_gpr[ret], t0, v1_t);
+ break;
+ case 1:
+ /* NM_SHRA_R_QB */
+ check_dspr2(ctx);
+ gen_helper_shra_r_qb(cpu_gpr[ret], t0, v1_t);
+ break;
+ }
+ break;
+ case NM_SHRL_PH:
+ check_dspr2(ctx);
+ tcg_gen_movi_tl(t0, v2 >> 1);
+ gen_helper_shrl_ph(cpu_gpr[ret], t0, v1_t);
+ break;
+ case NM_REPL_QB:
+ {
+ check_dsp(ctx);
+ target_long result;
+ imm = (ctx->opcode >> 13) & 0xFF;
+ result = (uint32_t)imm << 24 |
+ (uint32_t)imm << 16 |
+ (uint32_t)imm << 8 |
+ (uint32_t)imm;
+ result = (int32_t)result;
+ tcg_gen_movi_tl(cpu_gpr[ret], result);
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ tcg_temp_free(t0);
+ tcg_temp_free(v1_t);
+}
+
+
static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
{
int rt = (ctx->opcode >> 21) & 0x1f;
int rs = (ctx->opcode >> 16) & 0x1f;
+ int rd = (ctx->opcode >> 11) & 0x1f;
switch ((ctx->opcode >> 6) & 0x07) {
+ case NM_POOL32AXF_1:
+ {
+ int32_t op1 = (ctx->opcode >> 9) & 0x07;
+ gen_pool32axf_1_nanomips_insn(ctx, op1, rt, rs, rd);
+ }
+ break;
+ case NM_POOL32AXF_2:
+ {
+ int32_t op1 = (ctx->opcode >> 12) & 0x03;
+ gen_pool32axf_2_nanomips_insn(ctx, op1, rt, rs, rd);
+ }
+ break;
case NM_POOL32AXF_4:
+ {
+ int32_t op1 = (ctx->opcode >> 9) & 0x7f;
+ gen_pool32axf_4_nanomips_insn(ctx, op1, rt, rs, rd);
+ }
+ break;
case NM_POOL32AXF_5:
switch ((ctx->opcode >> 9) & 0x7f) {
case NM_CLO:
@@ -16948,6 +17693,12 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
+ case NM_POOL32AXF_7:
+ {
+ int32_t op1 = (ctx->opcode >> 9) & 0x7;
+ gen_pool32axf_7_nanomips_insn(ctx, op1, rt, rs, rd);
+ }
+ break;
default:
generate_exception_end(ctx, EXCP_RI);
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v4 23/55] target/mips: Add emulation of DSP ASE for nanoMIPS - part 3
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 23/55] target/mips: Add emulation of DSP ASE for nanoMIPS - part 3 Aleksandar Markovic
@ 2018-07-25 15:04 ` Aleksandar Markovic
0 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-25 15:04 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel@nongnu.org
Cc: laurent@vivier.eu, riku.voipio@iki.fi,
philippe.mathieu.daude@gmail.com, aurelien@aurel32.net,
richard.henderson@linaro.org, Stefan Markovic, Petar Jovanovic,
Paul Burton
> From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
> Sent: Tuesday, July 24, 2018 7:31 PM
> From: Stefan Markovic <smarkovic@wavecomp.com>
>
> Add emulation of DSP ASE instructions for nanoMIPS - part 3.
This patch should be further split into four or so patches - each dealing with a single instruction pool.
Also, DSP instruction pools should use NM_XXX opcodes in decoding phase, and only use OPC_XXX opcodes whet they call corresponding gen_XXX() function or correspondiong helper function. This is not the case for one of instruction pools from this patch, if I remember correctly.
Aleksandar M.
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v4 24/55] target/mips: Add handling of branch delay slots for nanoMIPS
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (22 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 23/55] target/mips: Add emulation of DSP ASE for nanoMIPS - part 3 Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 25/55] target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair Aleksandar Markovic
` (30 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Matthew Fortune <matthew.fortune@mips.com>
ISA mode bit (LSB of address) is no longer required but is also
masked to allow for tools transition. The flag has_isa_mode has the
key role in the implementation.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/translate.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a8fbbe6..1c86145 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1458,6 +1458,7 @@ typedef struct DisasContext {
bool mrp;
bool nan2008;
bool abs2008;
+ bool has_isa_mode;
} DisasContext;
#define DISAS_STOP DISAS_TARGET_0
@@ -4538,7 +4539,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
if (blink > 0) {
int post_delay = insn_bytes + delayslot_size;
- int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16);
+ int lowbit = ctx->has_isa_mode && !!(ctx->hflags & MIPS_HFLAG_M16);
tcg_gen_movi_tl(cpu_gpr[blink],
ctx->base.pc_next + post_delay + lowbit);
@@ -10991,7 +10992,8 @@ static void gen_branch(DisasContext *ctx, int insn_bytes)
break;
case MIPS_HFLAG_BR:
/* unconditional branch to register */
- if (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS)) {
+ if (ctx->has_isa_mode &&
+ (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS))) {
TCGv t0 = tcg_temp_new();
TCGv_i32 t1 = tcg_temp_new_i32();
@@ -11027,7 +11029,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
int bcond_compute = 0;
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
- int m16_lowbit = (ctx->hflags & MIPS_HFLAG_M16) != 0;
+ int m16_lowbit = ctx->has_isa_mode && ((ctx->hflags & MIPS_HFLAG_M16) != 0);
if (ctx->hflags & MIPS_HFLAG_BMASK) {
#ifdef MIPS_DEBUG_DISAS
@@ -24751,6 +24753,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
+ ctx->has_isa_mode = ((env->CP0_Config3 >> CP0C3_MMAR) & 0x7) != 3;
restore_cpu_state(env, ctx);
#ifdef CONFIG_USER_ONLY
ctx->mem_idx = MIPS_HFLAG_UM;
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 25/55] target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (23 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 24/55] target/mips: Add handling of branch delay slots for nanoMIPS Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 26/55] target/mips: Add updating BadInstr, BadInstrP, BadInstrX for nanoMIPS Aleksandar Markovic
` (29 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Yongbok Kim <yongbok.kim@mips.com>
Implement nanoMIPS LLWP and SCWP instruction pair.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
linux-user/mips/cpu_loop.c | 25 ++++++++---
target/mips/cpu.h | 2 +
target/mips/helper.h | 2 +
target/mips/op_helper.c | 35 +++++++++++++++
target/mips/translate.c | 109 +++++++++++++++++++++++++++++++++++++++++++++
5 files changed, 168 insertions(+), 5 deletions(-)
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index 084ad6a..1d3dc9e 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -397,10 +397,13 @@ static int do_store_exclusive(CPUMIPSState *env)
target_ulong addr;
target_ulong page_addr;
target_ulong val;
+ uint32_t val_wp = 0;
+ uint32_t llnewval_wp = 0;
int flags;
int segv = 0;
int reg;
int d;
+ int wp;
addr = env->lladdr;
page_addr = addr & TARGET_PAGE_MASK;
@@ -412,19 +415,31 @@ static int do_store_exclusive(CPUMIPSState *env)
} else {
reg = env->llreg & 0x1f;
d = (env->llreg & 0x20) != 0;
- if (d) {
- segv = get_user_s64(val, addr);
+ wp = (env->llreg & 0x40) != 0;
+ if (!wp) {
+ if (d) {
+ segv = get_user_s64(val, addr);
+ } else {
+ segv = get_user_s32(val, addr);
+ }
} else {
segv = get_user_s32(val, addr);
+ segv |= get_user_s32(val_wp, addr);
+ llnewval_wp = env->llnewval_wp;
}
if (!segv) {
- if (val != env->llval) {
+ if (val != env->llval && val_wp == llnewval_wp) {
env->active_tc.gpr[reg] = 0;
} else {
- if (d) {
- segv = put_user_u64(env->llnewval, addr);
+ if (!wp) {
+ if (d) {
+ segv = put_user_u64(env->llnewval, addr);
+ } else {
+ segv = put_user_u32(env->llnewval, addr);
+ }
} else {
segv = put_user_u32(env->llnewval, addr);
+ segv |= put_user_u32(env->llnewval_wp, addr + 4);
}
if (!segv) {
env->active_tc.gpr[reg] = 1;
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 009202c..2d341d7 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -506,6 +506,8 @@ struct CPUMIPSState {
uint64_t lladdr;
target_ulong llval;
target_ulong llnewval;
+ uint32_t llval_wp;
+ uint32_t llnewval_wp;
target_ulong llreg;
uint64_t CP0_LLAddr_rw_bitmask;
int CP0_LLAddr_shift;
diff --git a/target/mips/helper.h b/target/mips/helper.h
index b2a780a..deca307 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -14,6 +14,8 @@ DEF_HELPER_4(swr, void, env, tl, tl, int)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(ll, tl, env, tl, int)
DEF_HELPER_4(sc, tl, env, tl, tl, int)
+DEF_HELPER_5(llwp, void, env, tl, i32, i32, i32)
+DEF_HELPER_4(scwp, tl, env, tl, i64, int)
#ifdef TARGET_MIPS64
DEF_HELPER_3(lld, tl, env, tl, int)
DEF_HELPER_4(scd, tl, env, tl, tl, int)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index b3eef9f..cb83b6d 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -380,6 +380,19 @@ HELPER_LD_ATOMIC(lld, ld, 0x7)
#endif
#undef HELPER_LD_ATOMIC
+void helper_llwp(CPUMIPSState *env, target_ulong addr, uint32_t reg1,
+ uint32_t reg2, uint32_t mem_idx)
+{
+ if (addr & 0x7) {
+ env->CP0_BadVAddr = addr;
+ do_raise_exception(env, EXCP_AdEL, GETPC());
+ }
+ env->lladdr = do_translate_address(env, addr, 0, GETPC());
+ env->active_tc.gpr[reg1] = env->llval = do_lw(env, addr, mem_idx, GETPC());
+ env->active_tc.gpr[reg2] = env->llval_wp = do_lw(env, addr + 4, mem_idx,
+ GETPC());
+}
+
#define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
target_ulong arg2, int mem_idx) \
@@ -406,6 +419,28 @@ HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
#endif
#undef HELPER_ST_ATOMIC
+
+target_ulong helper_scwp(CPUMIPSState *env, target_ulong addr,
+ uint64_t data, int mem_idx)
+{
+ uint32_t tmp;
+ uint32_t tmp2;
+
+ if (addr & 0x7) {
+ env->CP0_BadVAddr = addr;
+ do_raise_exception(env, EXCP_AdES, GETPC());
+ }
+ if (do_translate_address(env, addr, 1, GETPC()) == env->lladdr) {
+ tmp = do_lw(env, addr, mem_idx, GETPC());
+ tmp2 = do_lw(env, addr + 4, mem_idx, GETPC());
+ if (tmp == env->llval && tmp2 == env->llval_wp) {
+ do_sw(env, addr, (uint32_t) data, mem_idx, GETPC());
+ do_sw(env, addr + 4, (uint32_t) *(&data + 4), mem_idx, GETPC());
+ return 1;
+ }
+ }
+ return 0;
+}
#endif
#ifdef TARGET_WORDS_BIGENDIAN
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 1c86145..cf28c60 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1459,6 +1459,7 @@ typedef struct DisasContext {
bool nan2008;
bool abs2008;
bool has_isa_mode;
+ bool xnp;
} DisasContext;
#define DISAS_STOP DISAS_TARGET_0
@@ -2336,6 +2337,44 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
tcg_temp_free(t0);
}
+static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset,
+ uint32_t reg1, uint32_t reg2)
+{
+#ifdef CONFIG_USER_ONLY
+ TCGv taddr = tcg_temp_new();
+ TCGv tval = tcg_temp_new();
+
+ gen_base_offset_addr(ctx, taddr, base, offset);
+ tcg_gen_qemu_ld32s(tval, taddr, ctx->mem_idx);
+ tcg_gen_st_tl(taddr, cpu_env, offsetof(CPUMIPSState, lladdr));
+ tcg_gen_st_tl(tval, cpu_env, offsetof(CPUMIPSState, llval));
+ tcg_gen_ext32s_tl(tval, tval);
+ gen_store_gpr(tval, reg1);
+
+ gen_base_offset_addr(ctx, taddr, base, offset + 4);
+ tcg_gen_qemu_ld32s(tval, taddr, ctx->mem_idx);
+ tcg_gen_st_tl(tval, cpu_env, offsetof(CPUMIPSState, llval_wp));
+ tcg_gen_ext32s_tl(tval, tval);
+ gen_store_gpr(tval, reg2);
+
+ tcg_temp_free(taddr);
+ tcg_temp_free(tval);
+#else
+ TCGv taddr = tcg_temp_new();
+ TCGv_i32 helper_mem_idx = tcg_const_i32(ctx->mem_idx);
+ TCGv_i32 helper_reg1 = tcg_const_i32(reg1);
+ TCGv_i32 helper_reg2 = tcg_const_i32(reg2);
+
+ gen_base_offset_addr(ctx, taddr, base, offset);
+ gen_helper_llwp(cpu_env, taddr, helper_reg1, helper_reg2, helper_mem_idx);
+
+ tcg_temp_free(taddr);
+ tcg_temp_free_i32(helper_mem_idx);
+ tcg_temp_free_i32(helper_reg1);
+ tcg_temp_free_i32(helper_reg2);
+#endif
+}
+
/* Store */
static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
int base, int offset)
@@ -2432,6 +2471,63 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
tcg_temp_free(t0);
}
+static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
+ uint32_t reg1, uint32_t reg2)
+{
+#ifdef CONFIG_USER_ONLY
+ TCGv taddr = tcg_temp_local_new();
+ TCGv t0 = tcg_temp_new();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
+
+ gen_base_offset_addr(ctx, taddr, base, offset);
+ tcg_gen_andi_tl(t0, taddr, 0x7);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
+ tcg_gen_st_tl(taddr, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
+ generate_exception(ctx, EXCP_AdES);
+ gen_set_label(l1);
+ tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr));
+ tcg_gen_brcond_tl(TCG_COND_NE, taddr, t0, l2);
+ tcg_gen_movi_tl(t0, reg1 | 0x60);
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, llreg));
+ gen_load_gpr(t0, reg1);
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, llnewval));
+ gen_load_gpr(t0, reg2);
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, llnewval_wp));
+ generate_exception_end(ctx, EXCP_SC);
+ gen_set_label(l2);
+ tcg_gen_movi_tl(t0, 0);
+ gen_store_gpr(t0, reg1);
+ tcg_temp_free(t0);
+ tcg_temp_free(taddr);
+#else
+ TCGv taddr = tcg_temp_new();
+ TCGv_i64 tdata = tcg_temp_new_i64();
+ TCGv_i32 helper_mem_idx = tcg_const_i32(ctx->mem_idx);
+
+ TCGv t0 = tcg_temp_new();
+ TCGv_i64 t1_64 = tcg_temp_new_i64();
+
+ gen_load_gpr(t0, reg2);
+ tcg_gen_ext_tl_i64(tdata, t0);
+ tcg_gen_shli_i64(tdata, tdata, 32);
+
+ gen_load_gpr(t0, reg1);
+ tcg_gen_ext_tl_i64(t1_64, t0);
+ tcg_gen_or_i64(tdata, tdata, t1_64);
+
+ gen_base_offset_addr(ctx, taddr, base, offset);
+ gen_helper_scwp(cpu_gpr[reg1], cpu_env, taddr, tdata, helper_mem_idx);
+
+ tcg_temp_free(taddr);
+ tcg_temp_free_i64(tdata);
+ tcg_temp_free_i32(helper_mem_idx);
+
+ tcg_temp_free(t0);
+ tcg_temp_free_i64(t1_64);
+#endif
+}
+
/* Load and store */
static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
TCGv t0)
@@ -19400,6 +19496,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_ld(ctx, OPC_LL, rt, rs, s);
break;
case NM_LLWP:
+ if (ctx->xnp) {
+ generate_exception_end(ctx, EXCP_RI);
+ } else {
+ gen_llwp(ctx, rs, 0, rt,
+ extract32(ctx->opcode, 3, 5));
+ }
break;
}
break;
@@ -19409,6 +19511,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_st_cond(ctx, OPC_SC, rt, rs, s);
break;
case NM_SCWP:
+ if (ctx->xnp) {
+ generate_exception_end(ctx, EXCP_RI);
+ } else {
+ gen_scwp(ctx, rs, 0, rt,
+ extract32(ctx->opcode, 3, 5));
+ }
break;
}
break;
@@ -24754,6 +24862,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
ctx->has_isa_mode = ((env->CP0_Config3 >> CP0C3_MMAR) & 0x7) != 3;
+ ctx->xnp = (env->CP0_Config5 >> CP0C5_XNP) & 1;
restore_cpu_state(env, ctx);
#ifdef CONFIG_USER_ONLY
ctx->mem_idx = MIPS_HFLAG_UM;
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 26/55] target/mips: Add updating BadInstr, BadInstrP, BadInstrX for nanoMIPS
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (24 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 25/55] target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 27/55] target/mips: Implement CP0 Config0.WR bit functionality Aleksandar Markovic
` (28 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Update BadInstr, BadInstrP,and BadInstrX registers for nanoMIPS.
The same support for pre-nanoMIPS remains unimplemented.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/helper.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index e215af9..b25e000 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -682,6 +682,31 @@ static void set_hflags_for_handler (CPUMIPSState *env)
static inline void set_badinstr_registers(CPUMIPSState *env)
{
+ if (env->insn_flags & ISA_NANOMIPS32) {
+ if (env->CP0_Config3 & (1 << CP0C3_BI)) {
+ uint32_t instr = (cpu_lduw_code(env, env->active_tc.PC)) << 16;
+ if ((instr & 0x10000000) == 0) {
+ instr |= cpu_lduw_code(env, env->active_tc.PC + 2);
+ }
+ env->CP0_BadInstr = instr;
+
+ if ((instr & 0xFC000000) == 0x60000000) {
+ instr = cpu_lduw_code(env, env->active_tc.PC + 4) << 16;
+ env->CP0_BadInstrX = instr;
+ }
+ }
+ if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
+ (env->hflags & MIPS_HFLAG_BMASK)) {
+ if (!(env->hflags & MIPS_HFLAG_B16)) {
+ env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
+ } else {
+ env->CP0_BadInstrP =
+ (cpu_lduw_code(env, env->active_tc.PC - 2)) << 16;
+ }
+ }
+ return;
+ }
+
if (env->hflags & MIPS_HFLAG_M16) {
/* TODO: add BadInstr support for microMIPS */
return;
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 27/55] target/mips: Implement CP0 Config0.WR bit functionality
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (25 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 26/55] target/mips: Add updating BadInstr, BadInstrP, BadInstrX for nanoMIPS Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 28/55] target/mips: Adjust behavior of Config3's ISAOnExc bit for nanoMIPS Aleksandar Markovic
` (27 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Stefan Markovic <smarkovic@wavecomp.com>
Add testing Config0.WR bit into watch exception handling logic.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/helper.c | 12 +++++++++++-
target/mips/translate.c | 22 ++++++++++++++++------
2 files changed, 27 insertions(+), 7 deletions(-)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index b25e000..a576fa4 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -747,6 +747,14 @@ void mips_cpu_do_interrupt(CPUState *cs)
(env->hflags & MIPS_HFLAG_DM)) {
cs->exception_index = EXCP_DINT;
}
+
+ if ((cs->exception_index == EXCP_DWATCH ||
+ cs->exception_index == EXCP_DFWATCH ||
+ cs->exception_index == EXCP_IWATCH) &&
+ (env->CP0_Config1 & (1 << CP0C1_WR))) {
+ cs->exception_index = EXCP_NONE;
+ }
+
offset = 0x180;
switch (cs->exception_index) {
case EXCP_DSS:
@@ -797,7 +805,9 @@ void mips_cpu_do_interrupt(CPUState *cs)
break;
case EXCP_SRESET:
env->CP0_Status |= (1 << CP0St_SR);
- memset(env->CP0_WatchLo, 0, sizeof(env->CP0_WatchLo));
+ if (env->CP0_Config1 & (1 << CP0C1_WR)) {
+ memset(env->CP0_WatchLo, 0, sizeof(env->CP0_WatchLo));
+ }
goto set_error_EPC;
case EXCP_NMI:
env->CP0_Status |= (1 << CP0St_NMI);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index cf28c60..68f1879 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5622,6 +5622,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -5639,6 +5640,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@@ -6321,6 +6323,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -6338,6 +6341,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@@ -7024,6 +7028,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(dmfc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -7041,6 +7046,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@@ -7705,6 +7711,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -7722,6 +7729,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@@ -25285,14 +25293,16 @@ void cpu_state_reset(CPUMIPSState *env)
no performance counters. */
env->CP0_IntCtl = 0xe0000000;
{
- int i;
+ if (env->CP0_Config1 & (1 << CP0C1_WR)) {
+ int i;
- for (i = 0; i < 7; i++) {
- env->CP0_WatchLo[i] = 0;
- env->CP0_WatchHi[i] = 0x80000000;
+ for (i = 0; i < 7; i++) {
+ env->CP0_WatchLo[i] = 0;
+ env->CP0_WatchHi[i] = 0x80000000;
+ }
+ env->CP0_WatchLo[7] = 0;
+ env->CP0_WatchHi[7] = 0;
}
- env->CP0_WatchLo[7] = 0;
- env->CP0_WatchHi[7] = 0;
}
/* Count register increments in debug mode, EJTAG version 1 */
env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 28/55] target/mips: Adjust behavior of Config3's ISAOnExc bit for nanoMIPS
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (26 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 27/55] target/mips: Implement CP0 Config0.WR bit functionality Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 29/55] target/mips: Adjust exception_resume_pc() " Aleksandar Markovic
` (26 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Yongbok Kim <yongbok.kim@mips.com>
Config3.ISAOnExc is read only in nanoMIPS.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/op_helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index cb83b6d..5e10286 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -1730,7 +1730,8 @@ void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
{
- if (env->insn_flags & ASE_MICROMIPS) {
+ if ((env->insn_flags & ASE_MICROMIPS) &&
+ !(env->insn_flags & ISA_NANOMIPS32)) {
env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
(arg1 & (1 << CP0C3_ISA_ON_EXC));
}
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 29/55] target/mips: Adjust exception_resume_pc() for nanoMIPS
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (27 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 28/55] target/mips: Adjust behavior of Config3's ISAOnExc bit for nanoMIPS Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 30/55] target/mips: Adjust set_hflags_for_handler() " Aleksandar Markovic
` (25 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: James Hogan <james.hogan@mips.com>
We shouldn't set the ISA bit in CP0_EPC for nanoMIPS.
Signed-off-by: James Hogan <james.hogan@mips.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index a576fa4..371fecf 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -656,7 +656,8 @@ target_ulong exception_resume_pc (CPUMIPSState *env)
target_ulong bad_pc;
target_ulong isa_mode;
- isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
+ isa_mode = env->hflags & MIPS_HFLAG_M16 &&
+ !(env->insn_flags & ISA_NANOMIPS32);
bad_pc = env->active_tc.PC | isa_mode;
if (env->hflags & MIPS_HFLAG_BMASK) {
/* If the exception was raised from a delay slot, come back to
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 30/55] target/mips: Adjust set_hflags_for_handler() for nanoMIPS
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (28 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 29/55] target/mips: Adjust exception_resume_pc() " Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 31/55] target/mips: Adjust set_pc() " Aleksandar Markovic
` (24 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: James Hogan <james.hogan@mips.com>
We shouldn't clear M16 mode when entering an interrupt on nanoMIPS,
otherwise we'll start interpreting the code as normal MIPS code.
Signed-off-by: James Hogan <james.hogan@mips.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index 371fecf..a734e86 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -671,6 +671,9 @@ target_ulong exception_resume_pc (CPUMIPSState *env)
#if !defined(CONFIG_USER_ONLY)
static void set_hflags_for_handler (CPUMIPSState *env)
{
+ if (env->insn_flags & ISA_NANOMIPS32) {
+ return;
+ }
/* Exception handlers are entered in 32-bit mode. */
env->hflags &= ~(MIPS_HFLAG_M16);
/* ...except that microMIPS lets you choose. */
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 31/55] target/mips: Adjust set_pc() for nanoMIPS
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (29 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 30/55] target/mips: Adjust set_hflags_for_handler() " Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 32/55] target/mips: Fix ERET/ERETNC behavior related to ADEL exception Aleksandar Markovic
` (23 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: James Hogan <james.hogan@mips.com>
ERET and ERETNC shouldn't clear MIPS_HFLAG_M16 for nanoMIPS since there
is no ISA bit, so fix set_pc() to skip the hflags update.
Signed-off-by: James Hogan <james.hogan@mips.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/op_helper.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 5e10286..c55a1e6 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -2428,6 +2428,10 @@ static void debug_post_eret(CPUMIPSState *env)
static void set_pc(CPUMIPSState *env, target_ulong error_pc)
{
env->active_tc.PC = error_pc & ~(target_ulong)1;
+ if (env->insn_flags & ISA_NANOMIPS32) {
+ /* Don't clear MIPS_HFLAG_M16 */
+ return;
+ }
if (error_pc & 1) {
env->hflags |= MIPS_HFLAG_M16;
} else {
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 32/55] target/mips: Fix ERET/ERETNC behavior related to ADEL exception
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (30 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 31/55] target/mips: Adjust set_pc() " Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 33/55] elf: Add nanoMIPS specific variations in ELF header fields Aleksandar Markovic
` (22 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Yongbok Kim <yongbok.kim@mips.com>
Fix ERET/ERETNC so that ADEL exception can be raised.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/op_helper.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index c55a1e6..e6749c5 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -2430,6 +2430,13 @@ static void set_pc(CPUMIPSState *env, target_ulong error_pc)
env->active_tc.PC = error_pc & ~(target_ulong)1;
if (env->insn_flags & ISA_NANOMIPS32) {
/* Don't clear MIPS_HFLAG_M16 */
+ if (error_pc & 1) {
+ if (!(env->hflags & MIPS_HFLAG_DM)) {
+ env->CP0_BadVAddr = error_pc;
+ }
+ env->active_tc.PC = error_pc;
+ do_raise_exception(env, EXCP_AdEL, 0);
+ }
return;
}
if (error_pc & 1) {
@@ -2467,10 +2474,12 @@ void helper_eretnc(CPUMIPSState *env)
void helper_deret(CPUMIPSState *env)
{
debug_pre_eret(env);
- set_pc(env, env->CP0_DEPC);
env->hflags &= ~MIPS_HFLAG_DM;
compute_hflags(env);
+
+ set_pc(env, env->CP0_DEPC);
+
debug_post_eret(env);
}
#endif /* !CONFIG_USER_ONLY */
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 33/55] elf: Add nanoMIPS specific variations in ELF header fields
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (31 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 32/55] target/mips: Fix ERET/ERETNC behavior related to ADEL exception Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 34/55] elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too Aleksandar Markovic
` (21 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Add nanoMIPS-related values in ELF header fields as specified in
nanoMIPS' "ELF ABI Supplement".
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
include/elf.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index 2c4fe7a..fff5967 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -62,6 +62,24 @@ typedef int64_t Elf64_Sxword;
#define EF_MIPS_NAN2008 0x00000400
#define EF_MIPS_ARCH 0xf0000000
+/* nanoMIPS architecture bits, EF_NANOMIPS_ARCH */
+#define EF_NANOMIPS_ARCH_32R6 0x00000000 /* 32-bit nanoMIPS Release 6 ISA */
+#define EF_NANOMIPS_ARCH_64R6 0x10000000 /* 62-bit nanoMIPS Release 6 ISA */
+
+/* nanoMIPS ABI bits, EF_NANOMIPS_ABI */
+#define EF_NANOMIPS_ABI_P32 0x00001000 /* 32-bit nanoMIPS ABI */
+#define EF_NANOMIPS_ABI_P64 0x00002000 /* 64-bit nanoMIPS ABI */
+
+/* nanoMIPS processor specific flags, e_flags */
+#define EF_NANOMIPS_LINKRELAX 0x00000001 /* Link-time relaxation */
+#define EF_NANOMIPS_PIC 0x00000002 /* Position independant code */
+#define EF_NANOMIPS_32BITMODE 0x00000004 /* 32-bit object for 64-bit arch. */
+#define EF_NANOMIPS_PID 0x00000008 /* Position independant data */
+#define EF_NANOMIPS_PCREL 0x00000010 /* PC-relative mode */
+#define EF_NANOMIPS_ABI 0x0000f000 /* nanoMIPS ABI */
+#define EF_NANOMIPS_MACH 0x00ff0000 /* Machine variant */
+#define EF_NANOMIPS_ARCH 0xf0000000 /* nanoMIPS architecture */
+
/* MIPS machine variant */
#define EF_MIPS_MACH_NONE 0x00000000 /* A standard MIPS implementation */
#define EF_MIPS_MACH_3900 0x00810000 /* Toshiba R3900 */
@@ -143,6 +161,8 @@ typedef int64_t Elf64_Sxword;
#define EM_RISCV 243 /* RISC-V */
+#define EM_NANOMIPS 249 /* Wave Computing nanoMIPS */
+
/*
* This is an interim value that we will use until the committee comes
* up with a final number.
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 34/55] elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (32 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 33/55] elf: Add nanoMIPS specific variations in ELF header fields Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 35/55] elf: Don't check FCR31_NAN2008 bit for nanoMIPS Aleksandar Markovic
` (20 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Starting from nanoMIPS introduction, machine variant can be
EM_MIPS or EM_NANOMIPS.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
linux-user/elfload.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index df07055..8638612 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -853,6 +853,8 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUPPCState *en
#endif
#define ELF_ARCH EM_MIPS
+#define elf_check_arch(x) ((x) == EM_MIPS || (x) == EM_NANOMIPS)
+
static inline void init_thread(struct target_pt_regs *regs,
struct image_info *infop)
{
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 35/55] elf: Don't check FCR31_NAN2008 bit for nanoMIPS
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (33 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 34/55] elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 36/55] mips_malta: Add basic nanoMIPS boot code for MIPS' Malta Aleksandar Markovic
` (19 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Aleksandar Markovic <amarkovic@wavecomp.com>
nanoMIPS is always NaN2008 compliant, and rules for checking
FCR31's NAN2008 bit are obsoleted.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
linux-user/mips/cpu_loop.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index 1d3dc9e..c9c20cf 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -747,6 +747,9 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
if (regs->cp0_epc & 1) {
env->hflags |= MIPS_HFLAG_M16;
}
+ if (env->insn_flags & ISA_NANOMIPS32) {
+ return;
+ }
if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
if ((env->active_fpu.fcr31_rw_bitmask &
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 36/55] mips_malta: Add basic nanoMIPS boot code for MIPS' Malta
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (34 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 35/55] elf: Don't check FCR31_NAN2008 bit for nanoMIPS Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 37/55] mips_malta: Setup GT64120 BARs in nanoMIPS bootloader Aleksandar Markovic
` (18 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Matthew Fortune <matthew.fortune@mips.com>
Added very very basic nanoMIPS boot code but this is hacked in
unconditionally currently.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
hw/mips/mips_malta.c | 75 +++++++++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 69 insertions(+), 6 deletions(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 3467451..4bc9036 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -620,6 +620,58 @@ static void network_init(PCIBus *pci_bus)
a2 - 32-bit address of the environment variables table
a3 - RAM size in bytes
*/
+static void write_bootloader_nanomips(uint8_t *base, int64_t run_addr,
+ int64_t kernel_entry)
+{
+ uint16_t *p;
+
+ /* Small bootloader */
+ p = (uint16_t *)base;
+
+#define NM_HI1(VAL) (((VAL) >> 16) & 0x1f)
+#define NM_HI2(VAL) \
+ (((VAL) & 0xf000) | (((VAL) >> 19) & 0xffc) | (((VAL) >> 31) & 0x1))
+#define NM_LO(VAL) ((VAL) & 0xfff)
+
+ stw_p(p++, 0x2800); stw_p(p++, 0x001c); /* bc to_here */
+ stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */
+ stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */
+ stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */
+ stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */
+ stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */
+ stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */
+ stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */
+
+ /* to_here: */
+ stw_p(p++, 0x0080); stw_p(p++, 0x0002); /* li a0,2 */
+ stw_p(p++, 0xe3a0 | NM_HI1(ENVP_ADDR - 64));
+ stw_p(p++, NM_HI2(ENVP_ADDR - 64));
+ /* lui sp,%hi(ENVP_ADDR - 64) */
+ stw_p(p++, 0x83bd); stw_p(p++, NM_LO(ENVP_ADDR - 64));
+ /* ori sp,sp,%lo(ENVP_ADDR - 64) */
+ stw_p(p++, 0xe0a0 | NM_HI1(ENVP_ADDR));
+ stw_p(p++, NM_HI2(ENVP_ADDR));
+ /* lui a1,%hi(ENVP_ADDR) */
+ stw_p(p++, 0x80a5); stw_p(p++, NM_LO(ENVP_ADDR));
+ /* ori a1,a1,%lo(ENVP_ADDR) */
+ stw_p(p++, 0xe0c0 | NM_HI1(ENVP_ADDR + 8));
+ stw_p(p++, NM_HI2(ENVP_ADDR + 8));
+ /* lui a2,%hi(ENVP_ADDR + 8) */
+ stw_p(p++, 0x80c6); stw_p(p++, NM_LO(ENVP_ADDR + 8));
+ /* ori a2,a2,%lo(ENVP_ADDR + 8) */
+ stw_p(p++, 0xe0e0 | NM_HI1(loaderparams.ram_low_size));
+ stw_p(p++, NM_HI2(loaderparams.ram_low_size));
+ /* lui a3,%hi(loaderparams.ram_low_size) */
+ stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size));
+ /* ori a3,a3,%lo(loaderparams.ram_low_size) */
+ stw_p(p++, 0xe320 | NM_HI1(kernel_entry));
+ stw_p(p++, NM_HI2(kernel_entry));
+ /* lui t9,%hi(kernel_entry) */
+ stw_p(p++, 0x8339); stw_p(p++, NM_LO(kernel_entry));
+ /* ori t9,t9,%lo(kernel_entry) */
+ stw_p(p++, 0x4bf9); stw_p(p++, 0x0000);
+ /* jalrc t8 */
+}
static void write_bootloader(uint8_t *base, int64_t run_addr,
int64_t kernel_entry)
@@ -813,10 +865,16 @@ static int64_t load_kernel (void)
NULL, (uint64_t *)&kernel_entry, NULL,
(uint64_t *)&kernel_high, big_endian, EM_MIPS, 1, 0);
if (kernel_size < 0) {
- error_report("could not load kernel '%s': %s",
- loaderparams.kernel_filename,
- load_elf_strerror(kernel_size));
- exit(1);
+ kernel_size = load_elf(loaderparams.kernel_filename,
+ cpu_mips_kseg0_to_phys, NULL,
+ (uint64_t *)&kernel_entry, NULL,
+ (uint64_t *)&kernel_high, big_endian, EM_NANOMIPS, 1, 0);
+ if (kernel_size < 0) {
+ error_report("could not load kernel '%s': %s",
+ loaderparams.kernel_filename,
+ load_elf_strerror(kernel_size));
+ exit(1);
+ }
}
/* Check where the kernel has been linked */
@@ -1096,8 +1154,13 @@ void mips_malta_init(MachineState *machine)
loaderparams.initrd_filename = initrd_filename;
kernel_entry = load_kernel();
- write_bootloader(memory_region_get_ram_ptr(bios),
- bootloader_run_addr, kernel_entry);
+ if (!cpu_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) {
+ write_bootloader(memory_region_get_ram_ptr(bios),
+ bootloader_run_addr, kernel_entry);
+ } else {
+ write_bootloader_nanomips(memory_region_get_ram_ptr(bios),
+ bootloader_run_addr, kernel_entry);
+ }
if (kvm_enabled()) {
/* Write the bootloader code @ the end of RAM, 1MB reserved */
write_bootloader(memory_region_get_ram_ptr(ram_low_preio) +
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 37/55] mips_malta: Setup GT64120 BARs in nanoMIPS bootloader
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (35 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 36/55] mips_malta: Add basic nanoMIPS boot code for MIPS' Malta Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 38/55] mips_malta: Fix semihosting argument passing for nanoMIPS bare metal Aleksandar Markovic
` (17 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Paul Burton <pburton@wavecomp.com>
Setup the GT64120 BARs in the nanoMIPS bootloader, in the same way that
they are setup in the MIPS32 bootloader. This is necessary for Linux to
be able to access peripherals, including the UART.
Signed-off-by: Paul Burton <pburton@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
hw/mips/mips_malta.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 4bc9036..d1a7c1f 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -664,6 +664,79 @@ static void write_bootloader_nanomips(uint8_t *base, int64_t run_addr,
/* lui a3,%hi(loaderparams.ram_low_size) */
stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size));
/* ori a3,a3,%lo(loaderparams.ram_low_size) */
+
+ /* Load BAR registers as done by YAMON */
+ stw_p(p++, 0xe040); stw_p(p++, 0x0681);
+ /* lui t1, %hi(0xb4000000) */
+#ifdef TARGET_WORDS_BIGENDIAN
+ stw_p(p++, 0xe020); stw_p(p++, 0x0be1);
+ /* lui t0, %hi(0xdf000000) */
+#else
+ stw_p(p++, 0x0020); stw_p(p++, 0x00df);
+ /* addiu[32] t0, $0, 0xdf */
+#endif
+ stw_p(p++, 0x8422); stw_p(p++, 0x9068);
+ /* sw t0, 0x68(t1) */
+
+ stw_p(p++, 0xe040); stw_p(p++, 0x077d);
+ /* lui t1, %hi(0xbbe00000) */
+#ifdef TARGET_WORDS_BIGENDIAN
+ stw_p(p++, 0xe020); stw_p(p++, 0x0801);
+ /* lui t0, %hi(0xc0000000) */
+#else
+ stw_p(p++, 0x0020); stw_p(p++, 0x00c0);
+ /* addiu[32] t0, $0, 0xc0 */
+#endif
+ stw_p(p++, 0x8422); stw_p(p++, 0x9048);
+ /* sw t0, 0x48(t1) */
+#ifdef TARGET_WORDS_BIGENDIAN
+ stw_p(p++, 0xe020); stw_p(p++, 0x0800);
+ /* lui t0, %hi(0x40000000) */
+#else
+ stw_p(p++, 0x0020); stw_p(p++, 0x0040);
+ /* addiu[32] t0, $0, 0x40 */
+#endif
+ stw_p(p++, 0x8422); stw_p(p++, 0x9050);
+ /* sw t0, 0x50(t1) */
+
+#ifdef TARGET_WORDS_BIGENDIAN
+ stw_p(p++, 0xe020); stw_p(p++, 0x0001);
+ /* lui t0, %hi(0x80000000) */
+#else
+ stw_p(p++, 0x0020); stw_p(p++, 0x0080);
+ /* addiu[32] t0, $0, 0x80 */
+#endif
+ stw_p(p++, 0x8422); stw_p(p++, 0x9058);
+ /* sw t0, 0x58(t1) */
+#ifdef TARGET_WORDS_BIGENDIAN
+ stw_p(p++, 0xe020); stw_p(p++, 0x07e0);
+ /* lui t0, %hi(0x3f000000) */
+#else
+ stw_p(p++, 0x0020); stw_p(p++, 0x003f);
+ /* addiu[32] t0, $0, 0x3f */
+#endif
+ stw_p(p++, 0x8422); stw_p(p++, 0x9060);
+ /* sw t0, 0x60(t1) */
+
+#ifdef TARGET_WORDS_BIGENDIAN
+ stw_p(p++, 0xe020); stw_p(p++, 0x0821);
+ /* lui t0, %hi(0xc1000000) */
+#else
+ stw_p(p++, 0x0020); stw_p(p++, 0x00c1);
+ /* addiu[32] t0, $0, 0xc1 */
+#endif
+ stw_p(p++, 0x8422); stw_p(p++, 0x9080);
+ /* sw t0, 0x80(t1) */
+#ifdef TARGET_WORDS_BIGENDIAN
+ stw_p(p++, 0xe020); stw_p(p++, 0x0bc0);
+ /* lui t0, %hi(0x5e000000) */
+#else
+ stw_p(p++, 0x0020); stw_p(p++, 0x005e);
+ /* addiu[32] t0, $0, 0x5e */
+#endif
+ stw_p(p++, 0x8422); stw_p(p++, 0x9088);
+ /* sw t0, 0x88(t1) */
+
stw_p(p++, 0xe320 | NM_HI1(kernel_entry));
stw_p(p++, NM_HI2(kernel_entry));
/* lui t9,%hi(kernel_entry) */
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 38/55] mips_malta: Fix semihosting argument passing for nanoMIPS bare metal
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (36 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 37/55] mips_malta: Setup GT64120 BARs in nanoMIPS bootloader Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 39/55] gdbstub: Disable handling of nanoMIPS ISA bit in the MIPS gdbstub Aleksandar Markovic
` (16 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
hw/mips/mips_malta.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index d1a7c1f..8bb1686 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -643,7 +643,12 @@ static void write_bootloader_nanomips(uint8_t *base, int64_t run_addr,
stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */
/* to_here: */
- stw_p(p++, 0x0080); stw_p(p++, 0x0002); /* li a0,2 */
+ if (semihosting_get_argc()) {
+ /* Preserve a0 content as arguments have been passed */
+ stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */
+ } else {
+ stw_p(p++, 0x0080); stw_p(p++, 0x0002); /* li a0,2 */
+ }
stw_p(p++, 0xe3a0 | NM_HI1(ENVP_ADDR - 64));
stw_p(p++, NM_HI2(ENVP_ADDR - 64));
/* lui sp,%hi(ENVP_ADDR - 64) */
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 39/55] gdbstub: Disable handling of nanoMIPS ISA bit in the MIPS gdbstub
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (37 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 38/55] mips_malta: Fix semihosting argument passing for nanoMIPS bare metal Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 40/55] gdbstub: Add XML support for GDB for nanoMIPS Aleksandar Markovic
` (15 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: James Hogan <james.hogan@mips.com>
nanoMIPS has no ISA bit in the PC, so remove the handling of the low bit
of the PC in the MIPS gdbstub for nanoMIPS. This prevents the PC being
read as e.g. 0xbfc00001, and prevents writing to the PC clearing
MIPS_HFLAG_M16.
Signed-off-by: James Hogan <james.hogan@mips.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/gdbstub.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c
index 18e0e6d..559b69f 100644
--- a/target/mips/gdbstub.c
+++ b/target/mips/gdbstub.c
@@ -60,7 +60,8 @@ int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
return gdb_get_regl(mem_buf, (int32_t)env->CP0_Cause);
case 37:
return gdb_get_regl(mem_buf, env->active_tc.PC |
- !!(env->hflags & MIPS_HFLAG_M16));
+ (!(env->insn_flags & ISA_NANOMIPS32) &&
+ env->hflags & MIPS_HFLAG_M16));
case 72:
return gdb_get_regl(mem_buf, 0); /* fp */
case 89:
@@ -131,10 +132,12 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
break;
case 37:
env->active_tc.PC = tmp & ~(target_ulong)1;
- if (tmp & 1) {
- env->hflags |= MIPS_HFLAG_M16;
- } else {
- env->hflags &= ~(MIPS_HFLAG_M16);
+ if (!(env->insn_flags & ISA_NANOMIPS32)) {
+ if (tmp & 1) {
+ env->hflags |= MIPS_HFLAG_M16;
+ } else {
+ env->hflags &= ~(MIPS_HFLAG_M16);
+ }
}
break;
case 72: /* fp, ignored */
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 40/55] gdbstub: Add XML support for GDB for nanoMIPS
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (38 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 39/55] gdbstub: Disable handling of nanoMIPS ISA bit in the MIPS gdbstub Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 41/55] target/mips: Add definition of nanoMIPS I7200 CPU Aleksandar Markovic
` (14 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Stefan Markovic <smarkovic@wavecomp.com>
Add XML support files for GDB for nanoMIPS.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
MAINTAINERS | 3 ++-
gdb-xml/nanomips-cp0.xml | 13 +++++++++++++
gdb-xml/nanomips-cpu.xml | 44 ++++++++++++++++++++++++++++++++++++++++++++
gdb-xml/nanomips-dsp.xml | 20 ++++++++++++++++++++
gdb-xml/nanomips-fpu.xml | 45 +++++++++++++++++++++++++++++++++++++++++++++
gdb-xml/nanomips-linux.xml | 20 ++++++++++++++++++++
6 files changed, 144 insertions(+), 1 deletion(-)
create mode 100644 gdb-xml/nanomips-cp0.xml
create mode 100644 gdb-xml/nanomips-cpu.xml
create mode 100644 gdb-xml/nanomips-dsp.xml
create mode 100644 gdb-xml/nanomips-fpu.xml
create mode 100644 gdb-xml/nanomips-linux.xml
diff --git a/MAINTAINERS b/MAINTAINERS
index 7130807..a4907d0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -190,6 +190,8 @@ M: Aurelien Jarno <aurelien@aurel32.net>
M: Aleksandar Markovic <amarkovic@wavecomp.com>
S: Maintained
F: target/mips/
+F: disas/mips.c
+F: gdb-xml/*ips*.xml
F: hw/mips/
F: hw/misc/mips_*
F: hw/intc/mips_gic.c
@@ -199,7 +201,6 @@ F: include/hw/misc/mips_*
F: include/hw/intc/mips_gic.h
F: include/hw/timer/mips_gictimer.h
F: tests/tcg/mips/
-F: disas/mips.c
Moxie
M: Anthony Green <green@moxielogic.com>
diff --git a/gdb-xml/nanomips-cp0.xml b/gdb-xml/nanomips-cp0.xml
new file mode 100644
index 0000000..8095dc6
--- /dev/null
+++ b/gdb-xml/nanomips-cp0.xml
@@ -0,0 +1,13 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2007-2015 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.nanomips.cp0">
+ <reg name="status" bitsize="32"/>
+ <reg name="badvaddr" bitsize="32"/>
+ <reg name="cause" bitsize="32"/>
+</feature>
diff --git a/gdb-xml/nanomips-cpu.xml b/gdb-xml/nanomips-cpu.xml
new file mode 100644
index 0000000..6bba224
--- /dev/null
+++ b/gdb-xml/nanomips-cpu.xml
@@ -0,0 +1,44 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2007-2015 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.nanomips.cpu">
+ <reg name="r0" bitsize="32" regnum="0"/>
+ <reg name="r1" bitsize="32"/>
+ <reg name="r2" bitsize="32"/>
+ <reg name="r3" bitsize="32"/>
+ <reg name="r4" bitsize="32"/>
+ <reg name="r5" bitsize="32"/>
+ <reg name="r6" bitsize="32"/>
+ <reg name="r7" bitsize="32"/>
+ <reg name="r8" bitsize="32"/>
+ <reg name="r9" bitsize="32"/>
+ <reg name="r10" bitsize="32"/>
+ <reg name="r11" bitsize="32"/>
+ <reg name="r12" bitsize="32"/>
+ <reg name="r13" bitsize="32"/>
+ <reg name="r14" bitsize="32"/>
+ <reg name="r15" bitsize="32"/>
+ <reg name="r16" bitsize="32"/>
+ <reg name="r17" bitsize="32"/>
+ <reg name="r18" bitsize="32"/>
+ <reg name="r19" bitsize="32"/>
+ <reg name="r20" bitsize="32"/>
+ <reg name="r21" bitsize="32"/>
+ <reg name="r22" bitsize="32"/>
+ <reg name="r23" bitsize="32"/>
+ <reg name="r24" bitsize="32"/>
+ <reg name="r25" bitsize="32"/>
+ <reg name="r26" bitsize="32"/>
+ <reg name="r27" bitsize="32"/>
+ <reg name="r28" bitsize="32"/>
+ <reg name="r29" bitsize="32"/>
+ <reg name="r30" bitsize="32"/>
+ <reg name="r31" bitsize="32"/>
+
+ <reg name="pc" bitsize="32"/>
+</feature>
diff --git a/gdb-xml/nanomips-dsp.xml b/gdb-xml/nanomips-dsp.xml
new file mode 100644
index 0000000..950910f
--- /dev/null
+++ b/gdb-xml/nanomips-dsp.xml
@@ -0,0 +1,20 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2012-2015 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.nanomips.dsp">
+ <reg name="hi0" bitsize="32"/>
+ <reg name="lo0" bitsize="32"/>
+ <reg name="hi1" bitsize="32"/>
+ <reg name="lo1" bitsize="32"/>
+ <reg name="hi2" bitsize="32"/>
+ <reg name="lo2" bitsize="32"/>
+ <reg name="hi3" bitsize="32"/>
+ <reg name="lo3" bitsize="32"/>
+
+ <reg name="dspctl" bitsize="32"/>
+</feature>
diff --git a/gdb-xml/nanomips-fpu.xml b/gdb-xml/nanomips-fpu.xml
new file mode 100644
index 0000000..fd225a5
--- /dev/null
+++ b/gdb-xml/nanomips-fpu.xml
@@ -0,0 +1,45 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2007-2015 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.nanomips.fpu">
+ <reg name="f0" bitsize="64" type="ieee_double"/>
+ <reg name="f1" bitsize="64" type="ieee_double"/>
+ <reg name="f2" bitsize="64" type="ieee_double"/>
+ <reg name="f3" bitsize="64" type="ieee_double"/>
+ <reg name="f4" bitsize="64" type="ieee_double"/>
+ <reg name="f5" bitsize="64" type="ieee_double"/>
+ <reg name="f6" bitsize="64" type="ieee_double"/>
+ <reg name="f7" bitsize="64" type="ieee_double"/>
+ <reg name="f8" bitsize="64" type="ieee_double"/>
+ <reg name="f9" bitsize="64" type="ieee_double"/>
+ <reg name="f10" bitsize="64" type="ieee_double"/>
+ <reg name="f11" bitsize="64" type="ieee_double"/>
+ <reg name="f12" bitsize="64" type="ieee_double"/>
+ <reg name="f13" bitsize="64" type="ieee_double"/>
+ <reg name="f14" bitsize="64" type="ieee_double"/>
+ <reg name="f15" bitsize="64" type="ieee_double"/>
+ <reg name="f16" bitsize="64" type="ieee_double"/>
+ <reg name="f17" bitsize="64" type="ieee_double"/>
+ <reg name="f18" bitsize="64" type="ieee_double"/>
+ <reg name="f19" bitsize="64" type="ieee_double"/>
+ <reg name="f20" bitsize="64" type="ieee_double"/>
+ <reg name="f21" bitsize="64" type="ieee_double"/>
+ <reg name="f22" bitsize="64" type="ieee_double"/>
+ <reg name="f23" bitsize="64" type="ieee_double"/>
+ <reg name="f24" bitsize="64" type="ieee_double"/>
+ <reg name="f25" bitsize="64" type="ieee_double"/>
+ <reg name="f26" bitsize="64" type="ieee_double"/>
+ <reg name="f27" bitsize="64" type="ieee_double"/>
+ <reg name="f28" bitsize="64" type="ieee_double"/>
+ <reg name="f29" bitsize="64" type="ieee_double"/>
+ <reg name="f30" bitsize="64" type="ieee_double"/>
+ <reg name="f31" bitsize="64" type="ieee_double"/>
+
+ <reg name="fcsr" bitsize="32" group="float"/>
+ <reg name="fir" bitsize="32" group="float"/>
+</feature>
diff --git a/gdb-xml/nanomips-linux.xml b/gdb-xml/nanomips-linux.xml
new file mode 100644
index 0000000..8a04634
--- /dev/null
+++ b/gdb-xml/nanomips-linux.xml
@@ -0,0 +1,20 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2007-2015 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>nanomips</architecture>
+ <osabi>GNU/Linux</osabi>
+ <xi:include href="nanomips-cpu.xml"/>
+ <xi:include href="nanomips-cp0.xml"/>
+ <xi:include href="nanomips-fpu.xml"/>
+ <xi:include href="nanomips-dsp.xml"/>
+
+ <feature name="org.gnu.gdb.nanomips.linux">
+ <reg name="restart" bitsize="32" group="system"/>
+ </feature>
+</target>
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 41/55] target/mips: Add definition of nanoMIPS I7200 CPU
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (39 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 40/55] gdbstub: Add XML support for GDB for nanoMIPS Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 42/55] linux-user: Add syscall numbers for nanoMIPS Aleksandar Markovic
` (13 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Stefan Markovic <smarkovic@wavecomp.com>
Add definition of the first nanoMIPS processor in QEMU.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/translate_init.inc.c | 40 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
index c7ba6ee..d3f32e8 100644
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.inc.c
@@ -449,6 +449,46 @@ const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,
.mmu_type = MMU_TYPE_R4000,
},
+ {
+ .name = "I7200",
+ .CP0_PRid = 0x00010000,
+ .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = (1U << CP0C1_M) | (15 << CP0C1_MMU) | (2 << CP0C1_IS) |
+ (4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS) |
+ (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) |
+ (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) |
+ (1 << CP0C3_BI) | (1 << CP0C3_SC) | (3 << CP0C3_MMAR) |
+ (1 << CP0C3_ISA_ON_EXC) | (1 << CP0C3_ISA) |
+ (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |
+ (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
+ (1 << CP0C3_CTXTC) | (1 << CP0C3_VInt) |
+ (1 << CP0C3_CDMM) | (1 << CP0C3_MT) | (1 << CP0C3_TL),
+ .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
+ (2 << CP0C4_IE) | (1U << CP0C4_M),
+ .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB),
+ .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
+ (1 << CP0C5_UFE),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 0,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x3158FF1F,
+ .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
+ (1U << CP0PG_RIE),
+ .CP0_PageGrain_rw_bitmask = 0,
+ .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
+ (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
+ (1 << FCR0_S) | (0x02 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_NANOMIPS32 | ASE_MICROMIPS | ASE_DSP | ASE_DSPR2 |
+ ASE_MT,
+ .mmu_type = MMU_TYPE_R4000,
+ },
#if defined(TARGET_MIPS64)
{
.name = "R4000",
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 42/55] linux-user: Add syscall numbers for nanoMIPS
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (40 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 41/55] target/mips: Add definition of nanoMIPS I7200 CPU Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 43/55] linux-user: Add target_signal.h header " Aleksandar Markovic
` (12 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Aleksandar Rikalo <arikalo@wavecomp.com>
Add syscall numbers for nanoMIPS. nanoMIPS redefines its ABI
compared to preceding MIPS architectures, and its set of
supported system calls is significantly different.
Signed-off-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
linux-user/nanomips/syscall_nr.h | 275 +++++++++++++++++++++++++++++++++++++++
1 file changed, 275 insertions(+)
create mode 100644 linux-user/nanomips/syscall_nr.h
diff --git a/linux-user/nanomips/syscall_nr.h b/linux-user/nanomips/syscall_nr.h
new file mode 100644
index 0000000..b826e5c
--- /dev/null
+++ b/linux-user/nanomips/syscall_nr.h
@@ -0,0 +1,275 @@
+/*
+ * Linux mipsp32 style syscalls.
+ */
+#define TARGET_NR_io_setup 0
+#define TARGET_NR_io_destroy 1
+#define TARGET_NR_io_submit 2
+#define TARGET_NR_io_cancel 3
+#define TARGET_NR_io_getevents 4
+#define TARGET_NR_setxattr 5
+#define TARGET_NR_lsetxattr 6
+#define TARGET_NR_fsetxattr 7
+#define TARGET_NR_getxattr 8
+#define TARGET_NR_lgetxattr 9
+#define TARGET_NR_fgetxattr 10
+#define TARGET_NR_listxattr 11
+#define TARGET_NR_llistxattr 12
+#define TARGET_NR_flistxattr 13
+#define TARGET_NR_removexattr 14
+#define TARGET_NR_lremovexattr 15
+#define TARGET_NR_fremovexattr 16
+#define TARGET_NR_getcwd 17
+#define TARGET_NR_lookup_dcookie 18
+#define TARGET_NR_eventfd2 19
+#define TARGET_NR_epoll_create1 20
+#define TARGET_NR_epoll_ctl 21
+#define TARGET_NR_epoll_pwait 22
+#define TARGET_NR_dup 23
+#define TARGET_NR_dup3 24
+#define TARGET_NR_fcntl64 25
+#define TARGET_NR_inotify_init1 26
+#define TARGET_NR_inotify_add_watch 27
+#define TARGET_NR_inotify_rm_watch 28
+#define TARGET_NR_ioctl 29
+#define TARGET_NR_ioprio_set 30
+#define TARGET_NR_ioprio_get 31
+#define TARGET_NR_flock 32
+#define TARGET_NR_mknodat 33
+#define TARGET_NR_mkdirat 34
+#define TARGET_NR_unlinkat 35
+#define TARGET_NR_symlinkat 36
+#define TARGET_NR_linkat 37
+#define TARGET_NR_umount2 39
+#define TARGET_NR_mount 40
+#define TARGET_NR_pivot_root 41
+#define TARGET_NR_nfsservctl 42
+#define TARGET_NR_statfs64 43
+#define TARGET_NR_fstatfs64 44
+#define TARGET_NR_truncate64 45
+#define TARGET_NR_ftruncate64 46
+#define TARGET_NR_fallocate 47
+#define TARGET_NR_faccessat 48
+#define TARGET_NR_chdir 49
+#define TARGET_NR_fchdir 50
+#define TARGET_NR_chroot 51
+#define TARGET_NR_fchmod 52
+#define TARGET_NR_fchmodat 53
+#define TARGET_NR_fchownat 54
+#define TARGET_NR_fchown 55
+#define TARGET_NR_openat 56
+#define TARGET_NR_close 57
+#define TARGET_NR_vhangup 58
+#define TARGET_NR_pipe2 59
+#define TARGET_NR_quotactl 60
+#define TARGET_NR_getdents64 61
+#define TARGET_NR__llseek 62
+#define TARGET_NR_read 63
+#define TARGET_NR_write 64
+#define TARGET_NR_readv 65
+#define TARGET_NR_writev 66
+#define TARGET_NR_pread64 67
+#define TARGET_NR_pwrite64 68
+#define TARGET_NR_preadv 69
+#define TARGET_NR_pwritev 70
+#define TARGET_NR_sendfile64 71
+#define TARGET_NR_pselect6 72
+#define TARGET_NR_ppoll 73
+#define TARGET_NR_signalfd4 74
+#define TARGET_NR_vmsplice 75
+#define TARGET_NR_splice 76
+#define TARGET_NR_tee 77
+#define TARGET_NR_readlinkat 78
+#define TARGET_NR_sync 81
+#define TARGET_NR_fsync 82
+#define TARGET_NR_fdatasync 83
+#define TARGET_NR_sync_file_range2 84
+#define TARGET_NR_timerfd_create 85
+#define TARGET_NR_timerfd_settime 86
+#define TARGET_NR_timerfd_gettime 87
+#define TARGET_NR_utimensat 88
+#define TARGET_NR_acct 89
+#define TARGET_NR_capget 90
+#define TARGET_NR_capset 91
+#define TARGET_NR_personality 92
+#define TARGET_NR_exit 93
+#define TARGET_NR_exit_group 94
+#define TARGET_NR_waitid 95
+#define TARGET_NR_set_tid_address 96
+#define TARGET_NR_unshare 97
+#define TARGET_NR_futex 98
+#define TARGET_NR_set_robust_list 99
+#define TARGET_NR_get_robust_list 100
+#define TARGET_NR_nanosleep 101
+#define TARGET_NR_getitimer 102
+#define TARGET_NR_setitimer 103
+#define TARGET_NR_kexec_load 104
+#define TARGET_NR_init_module 105
+#define TARGET_NR_delete_module 106
+#define TARGET_NR_timer_create 107
+#define TARGET_NR_timer_gettime 108
+#define TARGET_NR_timer_getoverrun 109
+#define TARGET_NR_timer_settime 110
+#define TARGET_NR_timer_delete 111
+#define TARGET_NR_clock_settime 112
+#define TARGET_NR_clock_gettime 113
+#define TARGET_NR_clock_getres 114
+#define TARGET_NR_clock_nanosleep 115
+#define TARGET_NR_syslog 116
+#define TARGET_NR_ptrace 117
+#define TARGET_NR_sched_setparam 118
+#define TARGET_NR_sched_setscheduler 119
+#define TARGET_NR_sched_getscheduler 120
+#define TARGET_NR_sched_getparam 121
+#define TARGET_NR_sched_setaffinity 122
+#define TARGET_NR_sched_getaffinity 123
+#define TARGET_NR_sched_yield 124
+#define TARGET_NR_sched_get_priority_max 125
+#define TARGET_NR_sched_get_priority_min 126
+#define TARGET_NR_sched_rr_get_interval 127
+#define TARGET_NR_restart_syscall 128
+#define TARGET_NR_kill 129
+#define TARGET_NR_tkill 130
+#define TARGET_NR_tgkill 131
+#define TARGET_NR_sigaltstack 132
+#define TARGET_NR_rt_sigsuspend 133
+#define TARGET_NR_rt_sigaction 134
+#define TARGET_NR_rt_sigprocmask 135
+#define TARGET_NR_rt_sigpending 136
+#define TARGET_NR_rt_sigtimedwait 137
+#define TARGET_NR_rt_sigqueueinfo 138
+#define TARGET_NR_rt_sigreturn 139
+#define TARGET_NR_setpriority 140
+#define TARGET_NR_getpriority 141
+#define TARGET_NR_reboot 142
+#define TARGET_NR_setregid 143
+#define TARGET_NR_setgid 144
+#define TARGET_NR_setreuid 145
+#define TARGET_NR_setuid 146
+#define TARGET_NR_setresuid 147
+#define TARGET_NR_getresuid 148
+#define TARGET_NR_setresgid 149
+#define TARGET_NR_getresgid 150
+#define TARGET_NR_setfsuid 151
+#define TARGET_NR_setfsgid 152
+#define TARGET_NR_times 153
+#define TARGET_NR_setpgid 154
+#define TARGET_NR_getpgid 155
+#define TARGET_NR_getsid 156
+#define TARGET_NR_setsid 157
+#define TARGET_NR_getgroups 158
+#define TARGET_NR_setgroups 159
+#define TARGET_NR_uname 160
+#define TARGET_NR_sethostname 161
+#define TARGET_NR_setdomainname 162
+#define TARGET_NR_getrusage 165
+#define TARGET_NR_umask 166
+#define TARGET_NR_prctl 167
+#define TARGET_NR_getcpu 168
+#define TARGET_NR_gettimeofday 169
+#define TARGET_NR_settimeofday 170
+#define TARGET_NR_adjtimex 171
+#define TARGET_NR_getpid 172
+#define TARGET_NR_getppid 173
+#define TARGET_NR_getuid 174
+#define TARGET_NR_geteuid 175
+#define TARGET_NR_getgid 176
+#define TARGET_NR_getegid 177
+#define TARGET_NR_gettid 178
+#define TARGET_NR_sysinfo 179
+#define TARGET_NR_mq_open 180
+#define TARGET_NR_mq_unlink 181
+#define TARGET_NR_mq_timedsend 182
+#define TARGET_NR_mq_timedreceive 183
+#define TARGET_NR_mq_notify 184
+#define TARGET_NR_mq_getsetattr 185
+#define TARGET_NR_msgget 186
+#define TARGET_NR_msgctl 187
+#define TARGET_NR_msgrcv 188
+#define TARGET_NR_msgsnd 189
+#define TARGET_NR_semget 190
+#define TARGET_NR_semctl 191
+#define TARGET_NR_semtimedop 192
+#define TARGET_NR_semop 193
+#define TARGET_NR_shmget 194
+#define TARGET_NR_shmctl 195
+#define TARGET_NR_shmat 196
+#define TARGET_NR_shmdt 197
+#define TARGET_NR_socket 198
+#define TARGET_NR_socketpair 199
+#define TARGET_NR_bind 200
+#define TARGET_NR_listen 201
+#define TARGET_NR_accept 202
+#define TARGET_NR_connect 203
+#define TARGET_NR_getsockname 204
+#define TARGET_NR_getpeername 205
+#define TARGET_NR_sendto 206
+#define TARGET_NR_recvfrom 207
+#define TARGET_NR_setsockopt 208
+#define TARGET_NR_getsockopt 209
+#define TARGET_NR_shutdown 210
+#define TARGET_NR_sendmsg 211
+#define TARGET_NR_recvmsg 212
+#define TARGET_NR_readahead 213
+#define TARGET_NR_brk 214
+#define TARGET_NR_munmap 215
+#define TARGET_NR_mremap 216
+#define TARGET_NR_add_key 217
+#define TARGET_NR_request_key 218
+#define TARGET_NR_keyctl 219
+#define TARGET_NR_clone 220
+#define TARGET_NR_execve 221
+#define TARGET_NR_mmap2 222
+#define TARGET_NR_fadvise64_64 223
+#define TARGET_NR_swapon 224
+#define TARGET_NR_swapoff 225
+#define TARGET_NR_mprotect 226
+#define TARGET_NR_msync 227
+#define TARGET_NR_mlock 228
+#define TARGET_NR_munlock 229
+#define TARGET_NR_mlockall 230
+#define TARGET_NR_munlockall 231
+#define TARGET_NR_mincore 232
+#define TARGET_NR_madvise 233
+#define TARGET_NR_remap_file_pages 234
+#define TARGET_NR_mbind 235
+#define TARGET_NR_get_mempolicy 236
+#define TARGET_NR_set_mempolicy 237
+#define TARGET_NR_migrate_pages 238
+#define TARGET_NR_move_pages 239
+#define TARGET_NR_rt_tgsigqueueinfo 240
+#define TARGET_NR_perf_event_open 241
+#define TARGET_NR_accept4 242
+#define TARGET_NR_recvmmsg 243
+#define TARGET_NR_set_thread_area 244
+#define TARGET_NR_wait4 260
+#define TARGET_NR_prlimit64 261
+#define TARGET_NR_fanotify_init 262
+#define TARGET_NR_fanotify_mark 263
+#define TARGET_NR_name_to_handle_at 264
+#define TARGET_NR_open_by_handle_at 265
+#define TARGET_NR_clock_adjtime 266
+#define TARGET_NR_syncfs 267
+#define TARGET_NR_setns 268
+#define TARGET_NR_sendmmsg 269
+#define TARGET_NR_process_vm_readv 270
+#define TARGET_NR_process_vm_writev 271
+#define TARGET_NR_kcmp 272
+#define TARGET_NR_finit_module 273
+#define TARGET_NR_sched_setattr 274
+#define TARGET_NR_sched_getattr 275
+#define TARGET_NR_renameat2 276
+#define TARGET_NR_seccomp 277
+#define TARGET_NR_getrandom 278
+#define TARGET_NR_memfd_create 279
+#define TARGET_NR_bpf 280
+#define TARGET_NR_execveat 281
+#define TARGET_NR_userfaultfd 282
+#define TARGET_NR_membarrier 283
+#define TARGET_NR_mlock2 284
+#define TARGET_NR_copy_file_range 285
+#define TARGET_NR_preadv2 286
+#define TARGET_NR_pwritev2 287
+#define TARGET_NR_pkey_mprotect 288
+#define TARGET_NR_pkey_alloc 289
+#define TARGET_NR_pkey_free 290
+#define TARGET_NR_statx 291
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 43/55] linux-user: Add target_signal.h header for nanoMIPS
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (41 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 42/55] linux-user: Add syscall numbers for nanoMIPS Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 44/55] linux-user: Add termbits.h " Aleksandar Markovic
` (11 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Aleksandar Rikalo <arikalo@wavecomp.com>
nanoMIPS signal handling is much closer to the signal handling in
other mainstream platforms that to the signal handling in preceding
MIPS platforms.
Signed-off-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
linux-user/nanomips/target_signal.h | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
create mode 100644 linux-user/nanomips/target_signal.h
diff --git a/linux-user/nanomips/target_signal.h b/linux-user/nanomips/target_signal.h
new file mode 100644
index 0000000..604e853
--- /dev/null
+++ b/linux-user/nanomips/target_signal.h
@@ -0,0 +1,22 @@
+#ifndef NANOMIPS_TARGET_SIGNAL_H
+#define NANOMIPS_TARGET_SIGNAL_H
+
+#include "../generic/signal.h"
+#undef TARGET_SIGRTMIN
+#define TARGET_SIGRTMIN 35
+
+/* this struct defines a stack used during syscall handling */
+typedef struct target_sigaltstack {
+ abi_long ss_sp;
+ abi_ulong ss_size;
+ abi_long ss_flags;
+} target_stack_t;
+
+/* sigaltstack controls */
+#define TARGET_SS_ONSTACK 1
+#define TARGET_SS_DISABLE 2
+
+#define TARGET_MINSIGSTKSZ 6144
+#define TARGET_SIGSTKSZ 12288
+
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 44/55] linux-user: Add termbits.h header for nanoMIPS
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (42 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 43/55] linux-user: Add target_signal.h header " Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 45/55] linux-user: Update syscall_defs.h " Aleksandar Markovic
` (10 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Aleksandar Rikalo <arikalo@wavecomp.com>
Add termbits.h header for nanoMIPS. Reuse MIPS' termbits.h as
the functionalities are almost identical.
Signed-off-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
linux-user/mips/termbits.h | 4 ++++
linux-user/nanomips/termbits.h | 1 +
2 files changed, 5 insertions(+)
create mode 100644 linux-user/nanomips/termbits.h
diff --git a/linux-user/mips/termbits.h b/linux-user/mips/termbits.h
index 49a72c5..c7254f4 100644
--- a/linux-user/mips/termbits.h
+++ b/linux-user/mips/termbits.h
@@ -1,6 +1,10 @@
/* from asm/termbits.h */
+#ifdef TARGET_NANOMIPS
+#define TARGET_NCCS 32
+#else
#define TARGET_NCCS 23
+#endif
struct target_termios {
unsigned int c_iflag; /* input mode flags */
diff --git a/linux-user/nanomips/termbits.h b/linux-user/nanomips/termbits.h
new file mode 100644
index 0000000..ea4e962
--- /dev/null
+++ b/linux-user/nanomips/termbits.h
@@ -0,0 +1 @@
+#include "../mips/termbits.h"
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 45/55] linux-user: Update syscall_defs.h header for nanoMIPS
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (43 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 44/55] linux-user: Add termbits.h " Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 46/55] linux-user: Add target_fcntl.h " Aleksandar Markovic
` (9 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Aleksandar Rikalo <arikalo@wavecomp.com>
Update constants and structures related to syscall support in
nanoMIPS.
Signed-off-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
linux-user/syscall_defs.h | 57 ++++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 52 insertions(+), 5 deletions(-)
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 40bb60e..abf94b8 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@ -374,7 +374,7 @@ struct target_dirent64 {
#define TARGET_SIG_IGN ((abi_long)1) /* ignore signal */
#define TARGET_SIG_ERR ((abi_long)-1) /* error return from signal */
-#ifdef TARGET_MIPS
+#if defined(TARGET_MIPS) && !defined(TARGET_NANOMIPS)
#define TARGET_NSIG 128
#else
#define TARGET_NSIG 64
@@ -445,7 +445,7 @@ struct target_sigaction {
target_sigset_t sa_mask;
abi_ulong sa_restorer;
};
-#elif defined(TARGET_MIPS)
+#elif defined(TARGET_MIPS) && !defined(TARGET_NANOMIPS)
struct target_sigaction {
uint32_t sa_flags;
#if defined(TARGET_ABI_MIPSN32)
@@ -459,6 +459,14 @@ struct target_sigaction {
abi_ulong sa_restorer;
#endif
};
+#elif defined(TARGET_NANOMIPS)
+struct target_sigaction {
+ abi_ulong _sa_handler;
+ abi_uint sa_flags;
+ target_sigset_t sa_mask;
+ abi_ulong sa_restorer;
+};
+
#else
struct target_old_sigaction {
abi_ulong _sa_handler;
@@ -537,7 +545,7 @@ typedef struct {
#define QEMU_SI_RT 5
typedef struct target_siginfo {
-#ifdef TARGET_MIPS
+#if defined(TARGET_MIPS) && !defined(TARGET_NANOMIPS)
int si_signo;
int si_code;
int si_errno;
@@ -665,13 +673,16 @@ struct target_rlimit {
#if defined(TARGET_ALPHA)
#define TARGET_RLIM_INFINITY 0x7fffffffffffffffull
-#elif defined(TARGET_MIPS) || (defined(TARGET_SPARC) && TARGET_ABI_BITS == 32)
+#elif (defined(TARGET_MIPS) && !defined(TARGET_NANOMIPS)) \
+ || (defined(TARGET_SPARC) && TARGET_ABI_BITS == 32)
#define TARGET_RLIM_INFINITY 0x7fffffffUL
+#elif defined(TARGET_NANOMIPS)
+#define TARGET_RLIM_INFINITY 0x76ffeec4UL
#else
#define TARGET_RLIM_INFINITY ((abi_ulong)-1)
#endif
-#if defined(TARGET_MIPS)
+#if defined(TARGET_MIPS) && !defined(TARGET_NANOMIPS)
#define TARGET_RLIMIT_CPU 0
#define TARGET_RLIMIT_FSIZE 1
#define TARGET_RLIMIT_DATA 2
@@ -687,6 +698,22 @@ struct target_rlimit {
#define TARGET_RLIMIT_MSGQUEUE 12
#define TARGET_RLIMIT_NICE 13
#define TARGET_RLIMIT_RTPRIO 14
+#elif defined(TARGET_NANOMIPS)
+#define TARGET_RLIMIT_CPU 0
+#define TARGET_RLIMIT_FSIZE 1
+#define TARGET_RLIMIT_DATA 2
+#define TARGET_RLIMIT_STACK 3
+#define TARGET_RLIMIT_CORE 4
+#define TARGET_RLIMIT_RSS 5
+#define TARGET_RLIMIT_NPROC 6
+#define TARGET_RLIMIT_NOFILE 7
+#define TARGET_RLIMIT_MEMLOCK 8
+#define TARGET_RLIMIT_AS 9
+#define TARGET_RLIMIT_LOCKS 10
+#define TARGET_RLIMIT_SIGPENDING 11
+#define TARGET_RLIMIT_MSGQUEUE 12
+#define TARGET_RLIMIT_NICE 13
+#define TARGET_RLIMIT_RTPRIO 14
#else
#define TARGET_RLIMIT_CPU 0
#define TARGET_RLIMIT_FSIZE 1
@@ -1657,6 +1684,10 @@ struct target_stat64 {
int64_t st_blocks;
};
+#elif defined(TARGET_ABI_MIPSP32)
+
+/* No struct stat and struct stat64 structures */
+
#elif defined(TARGET_ALPHA)
struct target_stat {
@@ -2009,6 +2040,22 @@ struct target_statfs {
int32_t f_flags;
int32_t f_spare[5];
};
+#elif defined(TARGET_ABI_MIPSP32)
+struct target_statfs {
+ abi_long f_type;
+ abi_long f_bsize;
+ abi_long f_blocks;
+ abi_long f_bfree;
+ abi_long f_bavail;
+ abi_long f_files;
+ abi_long f_ffree;
+
+ /* Linux specials */
+ target_fsid_t f_fsid;
+ abi_long f_namelen;
+ abi_llong f_frsize; /* Fragment size - unsupported */
+ abi_long f_spare[6];
+};
#else
struct target_statfs {
abi_long f_type;
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 46/55] linux-user: Add target_fcntl.h header for nanoMIPS
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (44 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 45/55] linux-user: Update syscall_defs.h " Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 47/55] linux-user: Add sockbits.h " Aleksandar Markovic
` (8 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Aleksandar Rikalo <arikalo@wavecomp.com>
Add fcntl-related constants and structures for nanoMIPS.
Signed-off-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
linux-user/nanomips/target_fcntl.h | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
create mode 100644 linux-user/nanomips/target_fcntl.h
diff --git a/linux-user/nanomips/target_fcntl.h b/linux-user/nanomips/target_fcntl.h
new file mode 100644
index 0000000..4203825
--- /dev/null
+++ b/linux-user/nanomips/target_fcntl.h
@@ -0,0 +1,38 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or (at your option) any
+ * later version. See the COPYING file in the top-level directory.
+ */
+
+#ifndef NANOMIPS_TARGET_FCNTL_H
+#define NANOMIPS_TARGET_FCNTL_H
+
+#define TARGET_O_APPEND 0x000400
+#define TARGET_O_DSYNC 0x001000
+#define TARGET_O_NONBLOCK 0x000800
+#define TARGET_O_CREAT 0x000040
+#define TARGET_O_TRUNC 0x000200
+#define TARGET_O_EXCL 0x000080
+#define TARGET_O_NOCTTY 0x000100
+#define TARGET_FASYNC 0x002000
+#define TARGET_O_LARGEFILE 0x008000
+#define TARGET___O_SYNC 0x101000
+#define TARGET_O_DIRECT 0x004000
+#define TARGET_O_CLOEXEC 0x080000
+
+#define TARGET_F_GETLK 5
+#define TARGET_F_SETLK 6
+#define TARGET_F_SETLKW 7
+#define TARGET_F_SETOWN 8 /* for sockets. */
+#define TARGET_F_GETOWN 9 /* for sockets. */
+
+#define TARGET_ARCH_FLOCK_PAD abi_long pad[4];
+#define TARGET_ARCH_FLOCK64_PAD
+
+#define TARGET_F_GETLK64 12 /* using 'struct flock64' */
+#define TARGET_F_SETLK64 13
+#define TARGET_F_SETLKW64 14
+
+#include "../generic/fcntl.h"
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 47/55] linux-user: Add sockbits.h header for nanoMIPS
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (45 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 46/55] linux-user: Add target_fcntl.h " Aleksandar Markovic
@ 2018-07-24 17:31 ` Aleksandar Markovic
2018-07-24 17:32 ` [Qemu-devel] [PATCH v4 48/55] linux-user: Add target_syscall.h " Aleksandar Markovic
` (7 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:31 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Aleksandar Rikalo <arikalo@wavecomp.com>
Add sockbits.h header for nanoMIPS.
Signed-off-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
linux-user/nanomips/sockbits.h | 1 +
1 file changed, 1 insertion(+)
create mode 100644 linux-user/nanomips/sockbits.h
diff --git a/linux-user/nanomips/sockbits.h b/linux-user/nanomips/sockbits.h
new file mode 100644
index 0000000..e6b6d31
--- /dev/null
+++ b/linux-user/nanomips/sockbits.h
@@ -0,0 +1 @@
+#include "../mips/sockbits.h"
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 48/55] linux-user: Add target_syscall.h header for nanoMIPS
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (46 preceding siblings ...)
2018-07-24 17:31 ` [Qemu-devel] [PATCH v4 47/55] linux-user: Add sockbits.h " Aleksandar Markovic
@ 2018-07-24 17:32 ` Aleksandar Markovic
2018-07-25 14:57 ` Aleksandar Markovic
2018-07-24 17:32 ` [Qemu-devel] [PATCH v4 49/55] linux-user: Add target_cpu.h " Aleksandar Markovic
` (6 subsequent siblings)
54 siblings, 1 reply; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:32 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Aleksandar Rikalo <arikalo@wavecomp.com>
Add target_syscall.h header for nanoMIPS.
Signed-off-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
linux-user/nanomips/target_syscall.h | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
create mode 100644 linux-user/nanomips/target_syscall.h
diff --git a/linux-user/nanomips/target_syscall.h b/linux-user/nanomips/target_syscall.h
new file mode 100644
index 0000000..b40e36b
--- /dev/null
+++ b/linux-user/nanomips/target_syscall.h
@@ -0,0 +1,30 @@
+/* this struct defines the way the registers are stored on the
+ stack during a system call. */
+
+struct target_pt_regs {
+ /* Pad bytes for argument save space on the stack. */
+ abi_ulong pad0[6];
+
+ /* Saved main processor registers. */
+ abi_ulong regs[32];
+
+ /* Saved special registers. */
+ abi_ulong cp0_status;
+ abi_ulong lo;
+ abi_ulong hi;
+ abi_ulong cp0_badvaddr;
+ abi_ulong cp0_cause;
+ abi_ulong cp0_epc;
+};
+
+/* Nasty hack: define a fake errno value for use by sigreturn. */
+#undef TARGET_QEMU_ESIGRETURN
+#define TARGET_QEMU_ESIGRETURN 255
+
+#define UNAME_MACHINE "nanomips"
+#define UNAME_MINIMUM_RELEASE "2.6.32"
+
+#define TARGET_CLONE_BACKWARDS
+#define TARGET_MINSIGSTKSZ 6144
+#define TARGET_MLOCKALL_MCL_CURRENT 1
+#define TARGET_MLOCKALL_MCL_FUTURE 2
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v4 48/55] linux-user: Add target_syscall.h header for nanoMIPS
2018-07-24 17:32 ` [Qemu-devel] [PATCH v4 48/55] linux-user: Add target_syscall.h " Aleksandar Markovic
@ 2018-07-25 14:57 ` Aleksandar Markovic
0 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-25 14:57 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel@nongnu.org
Cc: laurent@vivier.eu, riku.voipio@iki.fi,
philippe.mathieu.daude@gmail.com, aurelien@aurel32.net,
richard.henderson@linaro.org, Stefan Markovic, Petar Jovanovic,
Paul Burton
> From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
> Sent: Tuesday, July 24, 2018 7:32 PM
> From: Aleksandar Rikalo <arikalo@wavecomp.com>
>
> Add target_syscall.h header for nanoMIPS.
>
target_syscall.h is missing
#ifndef NANOMIPS_TARGET_SYSCALL_H
#define NANOMIPS_TARGET_SYSCALL_H
...
#endif
Aleksandar M.
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v4 49/55] linux-user: Add target_cpu.h header for nanoMIPS
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (47 preceding siblings ...)
2018-07-24 17:32 ` [Qemu-devel] [PATCH v4 48/55] linux-user: Add target_syscall.h " Aleksandar Markovic
@ 2018-07-24 17:32 ` Aleksandar Markovic
2018-07-24 17:32 ` [Qemu-devel] [PATCH v4 50/55] linux-user: Add target_structs.h " Aleksandar Markovic
` (5 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:32 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Dimitrije Nikolic <dnikolic@wavecomp.com>
Add target_cpu.h header for nanoMIPS.
Signed-off-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
linux-user/nanomips/target_cpu.h | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
create mode 100644 linux-user/nanomips/target_cpu.h
diff --git a/linux-user/nanomips/target_cpu.h b/linux-user/nanomips/target_cpu.h
new file mode 100644
index 0000000..bbb51de
--- /dev/null
+++ b/linux-user/nanomips/target_cpu.h
@@ -0,0 +1,21 @@
+#ifndef NANOMIPS_TARGET_CPU_H
+#define NANOMIPS_TARGET_CPU_H
+
+static inline void cpu_clone_regs(CPUMIPSState *env, target_ulong newsp)
+{
+ if (newsp) {
+ env->active_tc.gpr[29] = newsp;
+ }
+ env->active_tc.gpr[4] = 0;
+}
+
+static inline void cpu_set_tls(CPUMIPSState *env, target_ulong newtls)
+{
+ env->active_tc.CP0_UserLocal = newtls;
+}
+
+static inline abi_ulong get_sp_from_cpustate(CPUMIPSState *state)
+{
+ return state->active_tc.gpr[29];
+}
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 50/55] linux-user: Add target_structs.h header for nanoMIPS
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (48 preceding siblings ...)
2018-07-24 17:32 ` [Qemu-devel] [PATCH v4 49/55] linux-user: Add target_cpu.h " Aleksandar Markovic
@ 2018-07-24 17:32 ` Aleksandar Markovic
2018-07-24 17:32 ` [Qemu-devel] [PATCH v4 51/55] linux-user: Add target_elf.h " Aleksandar Markovic
` (4 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:32 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Dimitrije Nikolic <dnikolic@wavecomp.com>
Add target_structs.h header for nanoMIPS, that redirects to the
corresponding MIPS header.
Signed-off-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
linux-user/nanomips/target_structs.h | 1 +
1 file changed, 1 insertion(+)
create mode 100644 linux-user/nanomips/target_structs.h
diff --git a/linux-user/nanomips/target_structs.h b/linux-user/nanomips/target_structs.h
new file mode 100644
index 0000000..cc6c6ea
--- /dev/null
+++ b/linux-user/nanomips/target_structs.h
@@ -0,0 +1 @@
+#include "../mips/target_structs.h"
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 51/55] linux-user: Add target_elf.h header for nanoMIPS
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (49 preceding siblings ...)
2018-07-24 17:32 ` [Qemu-devel] [PATCH v4 50/55] linux-user: Add target_structs.h " Aleksandar Markovic
@ 2018-07-24 17:32 ` Aleksandar Markovic
2018-07-24 17:32 ` [Qemu-devel] [PATCH v4 52/55] linux-user: Add signal.c " Aleksandar Markovic
` (3 subsequent siblings)
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:32 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Dimitrije Nikolic <dnikolic@wavecomp.com>
This header includes common elf header, and adds cpu_get_model()
function.
Signed-off-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
linux-user/nanomips/target_elf.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
create mode 100644 linux-user/nanomips/target_elf.h
diff --git a/linux-user/nanomips/target_elf.h b/linux-user/nanomips/target_elf.h
new file mode 100644
index 0000000..ca68dab
--- /dev/null
+++ b/linux-user/nanomips/target_elf.h
@@ -0,0 +1,14 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or (at your option) any
+ * later version. See the COPYING file in the top-level directory.
+ */
+
+#ifndef NANOMIPS_TARGET_ELF_H
+#define NANOMIPS_TARGET_ELF_H
+static inline const char *cpu_get_model(uint32_t eflags)
+{
+ return "I7200";
+}
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 52/55] linux-user: Add signal.c for nanoMIPS
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (50 preceding siblings ...)
2018-07-24 17:32 ` [Qemu-devel] [PATCH v4 51/55] linux-user: Add target_elf.h " Aleksandar Markovic
@ 2018-07-24 17:32 ` Aleksandar Markovic
2018-07-25 14:52 ` Aleksandar Markovic
2018-07-24 17:32 ` [Qemu-devel] [PATCH v4 53/55] linux-user: Add cpu_loop.c " Aleksandar Markovic
` (2 subsequent siblings)
54 siblings, 1 reply; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:32 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Dimitrije Nikolic <dnikolic@wavecomp.com>
Add signal.c as a dredirection of regular mips' signal.c, but also
amend regular mips' signal.c. this is done to avoid the duplication
of large pieces of code.
Signed-off-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
linux-user/mips/signal.c | 36 +++++++++++++++++++++++++++++++-----
linux-user/nanomips/signal.c | 1 +
2 files changed, 32 insertions(+), 5 deletions(-)
create mode 100644 linux-user/nanomips/signal.c
diff --git a/linux-user/mips/signal.c b/linux-user/mips/signal.c
index 6aa303e..3d7bcbc 100644
--- a/linux-user/mips/signal.c
+++ b/linux-user/mips/signal.c
@@ -21,7 +21,15 @@
#include "signal-common.h"
#include "linux-user/trace.h"
-# if defined(TARGET_ABI_MIPSO32)
+#if defined(TARGET_ABI_MIPSP32)
+struct target_sigcontext {
+ uint64_t sc_regs[32];
+ uint64_t sc_pc;
+ uint32_t sc_used_math;
+ uint32_t sc_reserved;
+};
+#define TARGET_ALMASK (~15)
+#elif defined(TARGET_ABI_MIPSO32)
struct target_sigcontext {
uint32_t sc_regmask; /* Unused */
uint32_t sc_status;
@@ -43,6 +51,7 @@ struct target_sigcontext {
target_ulong sc_hi3;
target_ulong sc_lo3;
};
+#define TARGET_ALMASK (~7)
# else /* N32 || N64 */
struct target_sigcontext {
uint64_t sc_regs[32];
@@ -61,6 +70,7 @@ struct target_sigcontext {
uint32_t sc_dsp;
uint32_t sc_reserved;
};
+#define TARGET_ALMASK (~15)
# endif /* O32 */
struct sigframe {
@@ -91,6 +101,17 @@ static inline int install_sigtramp(unsigned int *tramp, unsigned int syscall)
{
int err = 0;
+#if defined(TARGET_ABI_MIPSP32)
+ uint16_t *tramp16 = (uint16_t *)tramp;
+ /*
+ * li $2, __NR__foo_sigreturn
+ * syscall 0
+ */
+ __put_user(0x6040 , tramp16 + 0);
+ __put_user(syscall, tramp16 + 1);
+ __put_user(0 , tramp16 + 2);
+ __put_user(0x1008 , tramp16 + 3);
+#else
/*
* Set up the return code ...
*
@@ -100,6 +121,7 @@ static inline int install_sigtramp(unsigned int *tramp, unsigned int syscall)
__put_user(0x24020000 + syscall, tramp + 0);
__put_user(0x0000000c , tramp + 1);
+#endif
return err;
}
@@ -116,6 +138,7 @@ static inline void setup_sigcontext(CPUMIPSState *regs,
__put_user(regs->active_tc.gpr[i], &sc->sc_regs[i]);
}
+#if !defined(TARGET_ABI_MIPSP32)
__put_user(regs->active_tc.HI[0], &sc->sc_mdhi);
__put_user(regs->active_tc.LO[0], &sc->sc_mdlo);
@@ -137,6 +160,7 @@ static inline void setup_sigcontext(CPUMIPSState *regs,
for (i = 0; i < 32; ++i) {
__put_user(regs->active_fpu.fpr[i].d, &sc->sc_fpregs[i]);
}
+#endif
}
static inline void
@@ -146,13 +170,14 @@ restore_sigcontext(CPUMIPSState *regs, struct target_sigcontext *sc)
__get_user(regs->CP0_EPC, &sc->sc_pc);
- __get_user(regs->active_tc.HI[0], &sc->sc_mdhi);
- __get_user(regs->active_tc.LO[0], &sc->sc_mdlo);
-
for (i = 1; i < 32; ++i) {
__get_user(regs->active_tc.gpr[i], &sc->sc_regs[i]);
}
+#if !defined(TARGET_ABI_MIPSP32)
+ __get_user(regs->active_tc.HI[0], &sc->sc_mdhi);
+ __get_user(regs->active_tc.LO[0], &sc->sc_mdlo);
+
__get_user(regs->active_tc.HI[1], &sc->sc_hi1);
__get_user(regs->active_tc.HI[2], &sc->sc_hi2);
__get_user(regs->active_tc.HI[3], &sc->sc_hi3);
@@ -168,6 +193,7 @@ restore_sigcontext(CPUMIPSState *regs, struct target_sigcontext *sc)
for (i = 0; i < 32; ++i) {
__get_user(regs->active_fpu.fpr[i].d, &sc->sc_fpregs[i]);
}
+#endif
}
/*
@@ -185,7 +211,7 @@ get_sigframe(struct target_sigaction *ka, CPUMIPSState *regs, size_t frame_size)
*/
sp = target_sigsp(get_sp_from_cpustate(regs) - 32, ka);
- return (sp - frame_size) & ~7;
+ return (sp - frame_size) & TARGET_ALMASK;
}
static void mips_set_hflags_isa_mode_from_pc(CPUMIPSState *env)
diff --git a/linux-user/nanomips/signal.c b/linux-user/nanomips/signal.c
new file mode 100644
index 0000000..86efc21
--- /dev/null
+++ b/linux-user/nanomips/signal.c
@@ -0,0 +1 @@
+#include "../mips/signal.c"
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v4 52/55] linux-user: Add signal.c for nanoMIPS
2018-07-24 17:32 ` [Qemu-devel] [PATCH v4 52/55] linux-user: Add signal.c " Aleksandar Markovic
@ 2018-07-25 14:52 ` Aleksandar Markovic
0 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-25 14:52 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel@nongnu.org
Cc: laurent@vivier.eu, riku.voipio@iki.fi,
philippe.mathieu.daude@gmail.com, aurelien@aurel32.net,
richard.henderson@linaro.org, Stefan Markovic, Petar Jovanovic,
Paul Burton
> From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
> Sent: Tuesday, July 24, 2018 7:32 PM
> From: Dimitrije Nikolic <dnikolic@wavecomp.com>
>
> Add signal.c as a dredirection of regular mips' signal.c, but also
> amend regular mips' signal.c. this is done to avoid the duplication
> of large pieces of code.
dredirection of -> redirection to
mips' -> MIPS'
this -> This
diff --git a/linux-user/mips/signal.c b/linux-user/mips/signal.c
index 6aa303e..3d7bcbc 100644
--- a/linux-user/mips/signal.c
+++ b/linux-user/mips/signal.c
@@ -21,7 +21,15 @@
#include "signal-common.h"
#include "linux-user/trace.h"
-# if defined(TARGET_ABI_MIPSO32)
+#if defined(TARGET_ABI_MIPSP32)
+struct target_sigcontext {
+ uint64_t sc_regs[32];
+ uint64_t sc_pc;
+ uint32_t sc_used_math;
+ uint32_t sc_reserved;
+};
+#define TARGET_ALMASK (~15)
+#elif defined(TARGET_ABI_MIPSO32)
struct target_sigcontext {
uint32_t sc_regmask; /* Unused */
uint32_t sc_status;
@@ -43,6 +51,7 @@ struct target_sigcontext {
target_ulong sc_hi3;
target_ulong sc_lo3;
};
+#define TARGET_ALMASK (~7)
# else /* N32 || N64 */
struct target_sigcontext {
uint64_t sc_regs[32];
@@ -61,6 +70,7 @@ struct target_sigcontext {
uint32_t sc_dsp;
uint32_t sc_reserved;
};
+#define TARGET_ALMASK (~15)
# endif /* O32 */
> struct sigframe {
> @@ -91,6 +101,17 @@ static inline int install_sigtramp(unsigned int *tramp, unsigned int syscall)
> {
> int err = 0;
>
> +#if defined(TARGET_ABI_MIPSP32)
> + uint16_t *tramp16 = (uint16_t *)tramp;
> + /*
> + * li $2, __NR__foo_sigreturn
> + * syscall 0
> + */
> + __put_user(0x6040 , tramp16 + 0);
> + __put_user(syscall, tramp16 + 1);
> + __put_user(0 , tramp16 + 2);
> + __put_user(0x1008 , tramp16 + 3);
> +#else
> /*
> * Set up the return code ...
> *
This code segment should be in a separate patch, called, let's say, "target/mips: Set up signal trampoline for nanoMIPS". Perhaps there should be one more patch "target/mips: Handle signal context for nanoMIPS", obtained in a similar fashion.
Aleksandar M.
^ permalink raw reply related [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v4 53/55] linux-user: Add cpu_loop.c for nanoMIPS
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (51 preceding siblings ...)
2018-07-24 17:32 ` [Qemu-devel] [PATCH v4 52/55] linux-user: Add signal.c " Aleksandar Markovic
@ 2018-07-24 17:32 ` Aleksandar Markovic
2018-07-24 17:32 ` [Qemu-devel] [PATCH v4 54/55] linux-user: Amend sigaction syscall support " Aleksandar Markovic
2018-07-24 17:32 ` [Qemu-devel] [PATCH v4 55/55] linux-user: Add nanoMIPS linux user mode configuration support Aleksandar Markovic
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:32 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Dimitrije Nikolic <dnikolic@wavecomp.com>
Amend regular MIPS' cpu_loop.c to include nanoMIPS support.
Signed-off-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
linux-user/mips/cpu_loop.c | 8 +++++++-
linux-user/nanomips/cpu_loop.c | 1 +
2 files changed, 8 insertions(+), 1 deletion(-)
create mode 100644 linux-user/nanomips/cpu_loop.c
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index c9c20cf..ada5a79 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -546,7 +546,7 @@ void cpu_loop(CPUMIPSState *env)
arg5, arg6, arg7, arg8);
}
done_syscall:
-# else
+# else /* N32/N64 and P32 */
ret = do_syscall(env, env->active_tc.gpr[2],
env->active_tc.gpr[4], env->active_tc.gpr[5],
env->active_tc.gpr[6], env->active_tc.gpr[7],
@@ -562,6 +562,7 @@ done_syscall:
Avoid clobbering register state. */
break;
}
+#if !defined(TARGET_ABI_MIPSP32)
if ((abi_ulong)ret >= (abi_ulong)-1133) {
env->active_tc.gpr[7] = 1; /* error flag */
ret = -ret;
@@ -569,6 +570,9 @@ done_syscall:
env->active_tc.gpr[7] = 0; /* error flag */
}
env->active_tc.gpr[2] = ret;
+#else
+ env->active_tc.gpr[4] = ret;
+#endif
break;
case EXCP_TLBL:
case EXCP_TLBS:
@@ -714,6 +718,8 @@ done_syscall:
} else {
code = ((trap_instr >> 6) & ((1 << 10) - 1));
}
+ } else if (env->insn_flags & ISA_NANOMIPS32) {
+ code = ((trap_instr >> 11) & ((1 << 5) - 1));
}
if (do_break(env, &info, code) != 0) {
diff --git a/linux-user/nanomips/cpu_loop.c b/linux-user/nanomips/cpu_loop.c
new file mode 100644
index 0000000..da4949a
--- /dev/null
+++ b/linux-user/nanomips/cpu_loop.c
@@ -0,0 +1 @@
+#include "../mips/cpu_loop.c"
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 54/55] linux-user: Amend sigaction syscall support for nanoMIPS
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (52 preceding siblings ...)
2018-07-24 17:32 ` [Qemu-devel] [PATCH v4 53/55] linux-user: Add cpu_loop.c " Aleksandar Markovic
@ 2018-07-24 17:32 ` Aleksandar Markovic
2018-07-24 17:32 ` [Qemu-devel] [PATCH v4 55/55] linux-user: Add nanoMIPS linux user mode configuration support Aleksandar Markovic
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:32 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Aleksandar Rikalo <arikalo@wavecomp.com>
Amend sigaction syscall support for nanoMIPS. This must be done
since nanoMIPS' signal handling is different than MIPS' signal
handling.
Signed-off-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
linux-user/syscall.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 3d57966..bced9b8 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -8825,7 +8825,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
old_act->sa_flags = oact.sa_flags;
unlock_user_struct(old_act, arg3, 1);
}
-#elif defined(TARGET_MIPS)
+#elif defined(TARGET_MIPS) && !defined(TARGET_NANOMIPS)
struct target_sigaction act, oact, *pact, *old_act;
if (arg2) {
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v4 55/55] linux-user: Add nanoMIPS linux user mode configuration support
2018-07-24 17:31 [Qemu-devel] [PATCH v4 00/55] Add nanoMIPS support to QEMU Aleksandar Markovic
` (53 preceding siblings ...)
2018-07-24 17:32 ` [Qemu-devel] [PATCH v4 54/55] linux-user: Amend sigaction syscall support " Aleksandar Markovic
@ 2018-07-24 17:32 ` Aleksandar Markovic
54 siblings, 0 replies; 65+ messages in thread
From: Aleksandar Markovic @ 2018-07-24 17:32 UTC (permalink / raw)
To: qemu-devel
Cc: laurent, riku.voipio, philippe.mathieu.daude, aurelien,
richard.henderson, amarkovic, smarkovic, pjovanovic, pburton
From: Stefan Markovic <smarkovic@wavecomp.com>
Add new linux user mode configuration for nanoMIPS.
Signed-off-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
configure | 13 ++++++++++++-
default-configs/nanomips-linux-user.mak | 1 +
2 files changed, 13 insertions(+), 1 deletion(-)
create mode 100644 default-configs/nanomips-linux-user.mak
diff --git a/configure b/configure
index 2a7796e..86c8b28 100755
--- a/configure
+++ b/configure
@@ -742,6 +742,9 @@ case "$cpu" in
supported_cpu="yes"
cross_cc_mips=$host_cc
;;
+ nanomips*)
+ cpu="mips"
+ ;;
sparc|sun4[cdmuv])
cpu="sparc"
supported_cpu="yes"
@@ -6883,7 +6886,7 @@ target_name=$(echo $target | cut -d '-' -f 1)
target_bigendian="no"
case "$target_name" in
- armeb|aarch64_be|hppa|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or1k|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
+ armeb|aarch64_be|hppa|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|nanomipseb|or1k|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
target_bigendian=yes
;;
esac
@@ -6999,6 +7002,11 @@ case "$target_name" in
moxie)
target_compiler=$cross_cc_moxie
;;
+ nanomips|nanomipseb)
+ TARGET_ARCH=nanomips
+ TARGET_BASE_ARCH=mips
+ echo "TARGET_ABI_MIPSP32=y" >> $config_target_mak
+ ;;
nios2)
target_compiler=$cross_cc_nios2
;;
@@ -7256,6 +7264,9 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
moxie*)
disas_config "MOXIE"
;;
+ nanomips*)
+ disas_config "MIPS"
+ ;;
nios2)
disas_config "NIOS2"
;;
diff --git a/default-configs/nanomips-linux-user.mak b/default-configs/nanomips-linux-user.mak
new file mode 100644
index 0000000..68fc1f7
--- /dev/null
+++ b/default-configs/nanomips-linux-user.mak
@@ -0,0 +1 @@
+# Default configuration for nanomips-linux-user
--
2.7.4
^ permalink raw reply related [flat|nested] 65+ messages in thread