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Thu, 13 Feb 2020 03:49:31 +0000 (UTC) Received: from localhost.localdomain (vpn2-54-95.bne.redhat.com [10.64.54.95]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 3E7B060499; Thu, 13 Feb 2020 03:49:24 +0000 (UTC) Subject: Re: [RESEND RFC PATCH v2 1/2] target/arm: Allow to inject SError interrupt To: Peter Maydell References: <20200205110541.37811-2-gshan@redhat.com> <8dce7dbe-c6c1-122a-f960-0fc29257dd1c@redhat.com> From: Gavin Shan Message-ID: <21e4051a-4d06-03cb-6d8e-5331b5b570c4@redhat.com> Date: Thu, 13 Feb 2020 14:49:21 +1100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-MC-Unique: lpd9mqrfPjGyNrAGruFQdA-1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Gavin Shan Cc: Andrew Jones , jthierry@redhat.com, Alexey Kardashevskiy , Marc Zyngier , Richard Henderson , QEMU Developers , Eric Auger , qemu-arm , Shan Gavin , Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/12/20 10:34 PM, Peter Maydell wrote: > On Wed, 12 Feb 2020 at 06:39, Gavin Shan wrote: >> On 2/5/20 10:05 PM, Gavin Shan wrote: >>> This allows to inject SError interrupt, which will be used on receiving >>> QMP/HMP "nmi" command in next patch. >>> >>> Signed-off-by: Gavin Shan >>> --- >>> target/arm/cpu.c | 11 +++++++++++ >>> target/arm/cpu.h | 12 +++++++++--- >>> target/arm/helper.c | 4 ++++ >>> 3 files changed, 24 insertions(+), 3 deletions(-) >>> >> >> Hi Peter, could you please take a look when you get a chance? I'm not sure >> the implementation is good enough to inject SError. If there are somebody >> else who can help to review, please let me know so that I can copy her/him >> either. > > Yeah, this is on my list to look at; Richard Henderson also could > have a look at it. From a quick scan I suspect you may be missing > handling for AArch32. > [Thanks for copying Richard Henderson] Yes, the functionality is only supported on aarch64 currently by intention because the next patch enables it on "max" and "host" CPU models and both of them are running in aarch64 mode. https://patchwork.kernel.org/patch/11366119/ If you really want to get this supported for aarch32 either, I can do it. However, it seems there is a long list of aarch32 CPU models, defined in target/arm/cpu.c::arm_cpus. so which CPU models you prefer to see with this supported? I think we might choose one or two popular CPU models if you agree. Thanks, Gavin