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[83.57.174.129]) by smtp.gmail.com with ESMTPSA id u7sm15390368wre.59.2019.10.23.04.18.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 23 Oct 2019 04:18:07 -0700 (PDT) Subject: Re: [PATCH v5 3/7] ppc/pnv: Introduce a PnvCore reset handler To: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , David Gibson References: <20191022163812.330-1-clg@kaod.org> <20191022163812.330-4-clg@kaod.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <21ea9a84-0a26-0ff7-c2a3-458c2c9016a1@redhat.com> Date: Wed, 23 Oct 2019 13:18:06 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: <20191022163812.330-4-clg@kaod.org> Content-Language: en-US X-MC-Unique: aJ0nrJWMP3yIUenkvceeaA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi C=C3=A9dric, On 10/22/19 6:38 PM, C=C3=A9dric Le Goater wrote: > in which individual CPUs are reset. It will ease the introduction of > future change reseting the interrupt presenter from the CPU reset > handler. >=20 > Signed-off-by: C=C3=A9dric Le Goater > Reviewed-by: Greg Kurz > --- > hw/ppc/pnv_core.c | 19 +++++++++++++++---- > 1 file changed, 15 insertions(+), 4 deletions(-) >=20 > diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c > index b1a7489e7abf..9f981a4940e6 100644 > --- a/hw/ppc/pnv_core.c > +++ b/hw/ppc/pnv_core.c > @@ -40,9 +40,8 @@ static const char *pnv_core_cpu_typename(PnvCore *pc) > return cpu_type; > } > =20 > -static void pnv_cpu_reset(void *opaque) > +static void pnv_core_cpu_reset(PowerPCCPU *cpu) > { > - PowerPCCPU *cpu =3D opaque; > CPUState *cs =3D CPU(cpu); > CPUPPCState *env =3D &cpu->env; > =20 > @@ -192,8 +191,17 @@ static void pnv_realize_vcpu(PowerPCCPU *cpu, PnvChi= p *chip, Error **errp) > =20 > /* Set time-base frequency to 512 MHz */ > cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); > +} > + > +static void pnv_core_reset(void *dev) Here the opaque pointer is a 'PnvCore *pc'. If you don't want to call it 'opaque', maybe 'pc' is better. > +{ > + CPUCore *cc =3D CPU_CORE(dev); > + PnvCore *pc =3D PNV_CORE(dev); This type conversion is not necessary. What about: static void pnv_core_reset(void *opaque) { PnvCore *pc =3D opaque; CPUCore *cc =3D CPU_CORE(pc); > + int i; > =20 > - qemu_register_reset(pnv_cpu_reset, cpu); > + for (i =3D 0; i < cc->nr_threads; i++) { > + pnv_core_cpu_reset(pc->threads[i]); > + } > } > =20 > static void pnv_core_realize(DeviceState *dev, Error **errp) > @@ -244,6 +252,8 @@ static void pnv_core_realize(DeviceState *dev, Error = **errp) > snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id); > pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops, > pc, name, PNV_XSCOM_EX_SIZE); > + > + qemu_register_reset(pnv_core_reset, pc); > return; > =20 > err: > @@ -259,7 +269,6 @@ static void pnv_unrealize_vcpu(PowerPCCPU *cpu) > { > PnvCPUState *pnv_cpu =3D pnv_cpu_state(cpu); > =20 > - qemu_unregister_reset(pnv_cpu_reset, cpu); > object_unparent(OBJECT(pnv_cpu_state(cpu)->intc)); > cpu_remove_sync(CPU(cpu)); > cpu->machine_data =3D NULL; > @@ -273,6 +282,8 @@ static void pnv_core_unrealize(DeviceState *dev, Erro= r **errp) > CPUCore *cc =3D CPU_CORE(dev); > int i; > =20 > + qemu_unregister_reset(pnv_core_reset, pc); > + > for (i =3D 0; i < cc->nr_threads; i++) { > pnv_unrealize_vcpu(pc->threads[i]); > } >=20