From: "Michael S. Tsirkin" <mst@redhat.com>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
Davidlohr Bueso <dave@stgolabs.net>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Fan Ni <fan.ni@samsung.com>
Subject: [PULL 55/63] hw/cxl/mbox: Add support for background operations
Date: Tue, 7 Nov 2023 05:13:30 -0500 [thread overview]
Message-ID: <221d2cfbdb5301f8f0cfbf26baf76544a5d71c27.1699351720.git.mst@redhat.com> (raw)
In-Reply-To: <cover.1699351720.git.mst@redhat.com>
From: Davidlohr Bueso <dave@stgolabs.net>
Support background commands in the mailbox, and update
cmd_infostat_bg_op_sts() accordingly. This patch does not implement mbox
interrupts upon completion, so the kernel driver must rely on polling to
know when the operation is done.
Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20231023160806.13206-12-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/cxl/cxl_device.h | 10 ++++
hw/cxl/cxl-device-utils.c | 24 ++++++++--
hw/cxl/cxl-mailbox-utils.c | 92 ++++++++++++++++++++++++++++++++++++-
3 files changed, 122 insertions(+), 4 deletions(-)
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index fa73ed03e5..124ff969ec 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -149,6 +149,16 @@ typedef struct CXLCCI {
} cel_log[1 << 16];
size_t cel_size;
+ /* background command handling (times in ms) */
+ struct {
+ uint16_t opcode;
+ uint16_t complete_pct;
+ uint16_t ret_code; /* Current value of retcode */
+ uint64_t starttime;
+ /* set by each bg cmd, cleared by the bg_timer when complete */
+ uint64_t runtime;
+ QEMUTimer *timer;
+ } bg;
size_t payload_max;
/* Pointer to device hosting the CCI */
DeviceState *d;
diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c
index f8938678c7..51466a626b 100644
--- a/hw/cxl/cxl-device-utils.c
+++ b/hw/cxl/cxl-device-utils.c
@@ -82,6 +82,25 @@ static uint64_t mailbox_reg_read(void *opaque, hwaddr offset, unsigned size)
case 4:
return cxl_dstate->mbox_reg_state32[offset / size];
case 8:
+ if (offset == A_CXL_DEV_BG_CMD_STS) {
+ uint64_t bg_status_reg;
+ bg_status_reg = FIELD_DP64(0, CXL_DEV_BG_CMD_STS, OP,
+ cci->bg.opcode);
+ bg_status_reg = FIELD_DP64(bg_status_reg, CXL_DEV_BG_CMD_STS,
+ PERCENTAGE_COMP, cci->bg.complete_pct);
+ bg_status_reg = FIELD_DP64(bg_status_reg, CXL_DEV_BG_CMD_STS,
+ RET_CODE, cci->bg.ret_code);
+ /* endian? */
+ cxl_dstate->mbox_reg_state64[offset / size] = bg_status_reg;
+ }
+ if (offset == A_CXL_DEV_MAILBOX_STS) {
+ uint64_t status_reg = cxl_dstate->mbox_reg_state64[offset / size];
+ if (cci->bg.complete_pct) {
+ status_reg = FIELD_DP64(status_reg, CXL_DEV_MAILBOX_STS, BG_OP,
+ 0);
+ cxl_dstate->mbox_reg_state64[offset / size] = status_reg;
+ }
+ }
return cxl_dstate->mbox_reg_state64[offset / size];
default:
g_assert_not_reached();
@@ -114,8 +133,7 @@ static void mailbox_mem_writeq(uint64_t *reg_state, hwaddr offset,
case A_CXL_DEV_MAILBOX_CMD:
break;
case A_CXL_DEV_BG_CMD_STS:
- /* BG not supported */
- /* fallthrough */
+ break;
case A_CXL_DEV_MAILBOX_STS:
/* Read only register, will get updated by the state machine */
return;
@@ -339,7 +357,7 @@ static void device_reg_init_common(CXLDeviceState *cxl_dstate)
static void mailbox_reg_init_common(CXLDeviceState *cxl_dstate)
{
- /* 2048 payload size, with no interrupt or background support */
+ /* 2048 payload size, with no interrupt */
ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP,
PAYLOAD_SIZE, CXL_MAILBOX_PAYLOAD_SHIFT);
cxl_dstate->payload_size = CXL_MAILBOX_MAX_PAYLOAD_SIZE;
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index de63fc1a28..f1226f8f39 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -963,6 +963,8 @@ static CXLRetCode cmd_media_clear_poison(const struct cxl_cmd *cmd,
#define IMMEDIATE_DATA_CHANGE (1 << 2)
#define IMMEDIATE_POLICY_CHANGE (1 << 3)
#define IMMEDIATE_LOG_CHANGE (1 << 4)
+#define SECURITY_STATE_CHANGE (1 << 5)
+#define BACKGROUND_OPERATION (1 << 6)
static const struct cxl_cmd cxl_cmd_set[256][256] = {
[EVENTS][GET_RECORDS] = { "EVENTS_GET_RECORDS",
@@ -1011,10 +1013,19 @@ static const struct cxl_cmd cxl_cmd_set_sw[256][256] = {
cmd_get_physical_port_state, ~0, 0 },
};
+/*
+ * While the command is executing in the background, the device should
+ * update the percentage complete in the Background Command Status Register
+ * at least once per second.
+ */
+
+#define CXL_MBOX_BG_UPDATE_FREQ 1000UL
+
int cxl_process_cci_message(CXLCCI *cci, uint8_t set, uint8_t cmd,
size_t len_in, uint8_t *pl_in, size_t *len_out,
uint8_t *pl_out, bool *bg_started)
{
+ int ret;
const struct cxl_cmd *cxl_cmd;
opcode_handler h;
@@ -1031,7 +1042,81 @@ int cxl_process_cci_message(CXLCCI *cci, uint8_t set, uint8_t cmd,
return CXL_MBOX_INVALID_PAYLOAD_LENGTH;
}
- return (*h)(cxl_cmd, pl_in, len_in, pl_out, len_out, cci);
+ /* Only one bg command at a time */
+ if ((cxl_cmd->effect & BACKGROUND_OPERATION) &&
+ cci->bg.runtime > 0) {
+ return CXL_MBOX_BUSY;
+ }
+
+ ret = (*h)(cxl_cmd, pl_in, len_in, pl_out, len_out, cci);
+ if ((cxl_cmd->effect & BACKGROUND_OPERATION) &&
+ ret == CXL_MBOX_BG_STARTED) {
+ *bg_started = true;
+ } else {
+ *bg_started = false;
+ }
+
+ /* Set bg and the return code */
+ if (*bg_started) {
+ uint64_t now;
+
+ cci->bg.opcode = (set << 8) | cmd;
+
+ cci->bg.complete_pct = 0;
+ cci->bg.ret_code = 0;
+
+ now = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
+ cci->bg.starttime = now;
+ timer_mod(cci->bg.timer, now + CXL_MBOX_BG_UPDATE_FREQ);
+ }
+
+ return ret;
+}
+
+static void bg_timercb(void *opaque)
+{
+ CXLCCI *cci = opaque;
+ CXLDeviceState *cxl_dstate = &CXL_TYPE3(cci->d)->cxl_dstate;
+ uint64_t bg_status_reg = 0;
+ uint64_t now = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
+ uint64_t total_time = cci->bg.starttime + cci->bg.runtime;
+
+ assert(cci->bg.runtime > 0);
+ bg_status_reg = FIELD_DP64(bg_status_reg, CXL_DEV_BG_CMD_STS,
+ OP, cci->bg.opcode);
+
+ if (now >= total_time) { /* we are done */
+ uint64_t status_reg;
+ uint16_t ret = CXL_MBOX_SUCCESS;
+
+ cci->bg.complete_pct = 100;
+ /* Clear bg */
+ status_reg = FIELD_DP64(0, CXL_DEV_MAILBOX_STS, BG_OP, 0);
+ cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_STS] = status_reg;
+
+ bg_status_reg = FIELD_DP64(bg_status_reg, CXL_DEV_BG_CMD_STS,
+ RET_CODE, ret);
+
+ /* TODO add ad-hoc cmd succesful completion handling */
+
+ qemu_log("Background command %04xh finished: %s\n",
+ cci->bg.opcode,
+ ret == CXL_MBOX_SUCCESS ? "success" : "aborted");
+ } else {
+ /* estimate only */
+ cci->bg.complete_pct = 100 * now / total_time;
+ timer_mod(cci->bg.timer, now + CXL_MBOX_BG_UPDATE_FREQ);
+ }
+
+ bg_status_reg = FIELD_DP64(bg_status_reg, CXL_DEV_BG_CMD_STS,
+ PERCENTAGE_COMP, cci->bg.complete_pct);
+ cxl_dstate->mbox_reg_state64[R_CXL_DEV_BG_CMD_STS] = bg_status_reg;
+
+ if (cci->bg.complete_pct == 100) {
+ cci->bg.starttime = 0;
+ /* registers are updated, allow new bg-capable cmds */
+ cci->bg.runtime = 0;
+ }
}
void cxl_init_cci(CXLCCI *cci, size_t payload_max)
@@ -1050,6 +1135,11 @@ void cxl_init_cci(CXLCCI *cci, size_t payload_max)
}
}
}
+ cci->bg.complete_pct = 0;
+ cci->bg.starttime = 0;
+ cci->bg.runtime = 0;
+ cci->bg.timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,
+ bg_timercb, cci);
}
void cxl_initialize_mailbox_swcci(CXLCCI *cci, DeviceState *intf,
--
MST
next prev parent reply other threads:[~2023-11-07 10:20 UTC|newest]
Thread overview: 73+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-07 10:09 [PULL 00/63] virtio,pc,pci: features, fixes Michael S. Tsirkin
2023-11-07 10:09 ` [PULL 01/63] vhost-user.rst: Improve [GS]ET_VRING_BASE doc Michael S. Tsirkin
2023-11-07 10:09 ` [PULL 02/63] vhost-user.rst: Clarify enabling/disabling vrings Michael S. Tsirkin
2023-11-07 10:09 ` [PULL 03/63] vhost-user.rst: Introduce suspended state Michael S. Tsirkin
2023-11-07 10:09 ` [PULL 04/63] vhost-user.rst: Migrating back-end-internal state Michael S. Tsirkin
2023-11-07 10:09 ` [PULL 05/63] vhost-user: Interface for migration state transfer Michael S. Tsirkin
2023-11-07 10:09 ` [PULL 06/63] vhost: Add high-level state save/load functions Michael S. Tsirkin
2023-11-07 10:09 ` [PULL 07/63] vhost-user-fs: Implement internal migration Michael S. Tsirkin
2023-11-07 10:09 ` [PULL 08/63] Add virtio-sound device stub Michael S. Tsirkin
2023-11-09 14:30 ` Peter Maydell
2023-11-09 15:50 ` Manos Pitsidianakis
2023-11-09 16:06 ` Peter Maydell
2023-11-09 16:10 ` Alex Bennée
2023-11-07 10:10 ` [PULL 09/63] Add virtio-sound-pci device Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 10/63] virtio-sound: handle control messages and streams Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 11/63] virtio-sound: handle VIRTIO_SND_R_PCM_INFO request Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 12/63] virtio-sound: handle VIRTIO_SND_R_PCM_{START,STOP} Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 13/63] virtio-sound: handle VIRTIO_SND_R_PCM_SET_PARAMS Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 14/63] virtio-sound: handle VIRTIO_SND_R_PCM_PREPARE Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 15/63] virtio-sound: handle VIRTIO_SND_R_PCM_RELEASE Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 16/63] virtio-sound: implement audio output (TX) Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 17/63] virtio-sound: implement audio capture (RX) Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 18/63] docs/system: add basic virtio-snd documentation Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 19/63] vdpa: Restore hash calculation state Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 20/63] vdpa: Allow VIRTIO_NET_F_HASH_REPORT in SVQ Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 21/63] vdpa: Add SetSteeringEBPF method for NetClientState Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 22/63] vdpa: Restore receive-side scaling state Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 23/63] vdpa: Allow VIRTIO_NET_F_RSS in SVQ Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 24/63] tests: test-smp-parse: Add the test for cores/threads per socket helpers Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 25/63] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 count test Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 26/63] tests: bios-tables-test: Add test for smbios type4 count Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 27/63] tests: bios-tables-test: Add ACPI table binaries for smbios type4 count test Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 28/63] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core " Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 29/63] tests: bios-tables-test: Add test for smbios type4 core count Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 30/63] tests: bios-tables-test: Add ACPI table binaries for smbios type4 core count test Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 31/63] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core count2 test Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 32/63] tests: bios-tables-test: Extend smbios core count2 test to cover general topology Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 33/63] tests: bios-tables-test: Update ACPI table binaries for smbios core count2 test Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 34/63] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 thread count test Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 35/63] tests: bios-tables-test: Add test for smbios type4 thread count Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 36/63] tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count test Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 37/63] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 thread count2 test Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 38/63] tests: bios-tables-test: Add test for smbios type4 thread count2 Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 39/63] tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count2 test Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 40/63] hw/cxl: Use a switch to explicitly check size in caps_reg_read() Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 41/63] hw/cxl: Use switch statements for read and write of cachemem registers Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 42/63] hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExt Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 43/63] hw/cxl: Line length reductions Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 44/63] hw/cxl: Fix a QEMU_BUILD_BUG_ON() in switch statement scope issue Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 45/63] hw/cxl/mbox: Pull the payload out of struct cxl_cmd and make instances constant Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 46/63] hw/cxl/mbox: Split mailbox command payload into separate input and output Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 47/63] hw/cxl/mbox: Pull the CCI definition out of the CXLDeviceState Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 48/63] hw/cxl/mbox: Generalize the CCI command processing Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 49/63] hw/pci-bridge/cxl_upstream: Move defintion of device to header Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 50/63] hw/cxl: Add a switch mailbox CCI function Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 51/63] hw/cxl/mbox: Add Information and Status / Identify command Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 52/63] hw/cxl/mbox: Add Physical Switch " Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 53/63] hw/pci-bridge/cxl_downstream: Set default link width and link speed Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 54/63] hw/cxl: Implement Physical Ports status retrieval Michael S. Tsirkin
2023-11-07 10:13 ` Michael S. Tsirkin [this message]
2023-11-09 14:44 ` [PULL 55/63] hw/cxl/mbox: Add support for background operations Peter Maydell
2023-11-10 4:25 ` Davidlohr Bueso
2023-11-07 10:13 ` [PULL 56/63] hw/cxl/mbox: Wire up interrupts for background completion Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 57/63] hw/cxl: Add support for device sanitation Michael S. Tsirkin
2023-11-09 14:39 ` Peter Maydell
2023-11-10 4:14 ` Davidlohr Bueso
2023-11-07 10:13 ` [PULL 58/63] hw/cxl/mbox: Add Get Background Operation Status Command Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 59/63] hw/cxl/type3: Cleanup multiple CXL_TYPE3() calls in read/write functions Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 60/63] hw/cxl: Add dummy security state get Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 61/63] hw/cxl: Add tunneled command support to mailbox for switch cci Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 62/63] acpi/tests/avocado/bits: enforce 32-bit SMBIOS entry point Michael S. Tsirkin
2023-11-07 10:14 ` [PULL 63/63] acpi/tests/avocado/bits: enable console logging from bits VM Michael S. Tsirkin
2023-11-07 13:40 ` [PULL 00/63] virtio,pc,pci: features, fixes Stefan Hajnoczi
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