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Wed, 21 Jun 2023 04:06:35 -0700 (PDT) Message-ID: <227914fb-3251-648e-799f-495273cd311f@linaro.org> Date: Wed, 21 Jun 2023 13:06:33 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH v3 8/8] target/tricore: Fix ICR.IE offset in RESTORE insn Content-Language: en-US To: Bastian Koppelmann , qemu-devel@nongnu.org References: <20230621101950.1645420-1-kbastian@mail.uni-paderborn.de> <20230621101950.1645420-9-kbastian@mail.uni-paderborn.de> From: Richard Henderson In-Reply-To: <20230621101950.1645420-9-kbastian@mail.uni-paderborn.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.093, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/21/23 12:19, Bastian Koppelmann wrote: > from ISA v1.6.1 onwards the bit position of ICR.IE changed. > ctx->icr_ie_offset contains the correct value for the ISA version used > by the vCPU. > > Reviewed-by: Richard Henderson > Signed-off-by: Bastian Koppelmann > --- > target/tricore/translate.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/target/tricore/translate.c b/target/tricore/translate.c > index 71b6209af4..9cab0734dd 100644 > --- a/target/tricore/translate.c > +++ b/target/tricore/translate.c > @@ -7956,7 +7956,8 @@ static void decode_sys_interrupts(DisasContext *ctx) > case OPC2_32_SYS_RESTORE: > if (has_feature(ctx, TRICORE_FEATURE_16)) { > if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) { > - tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1); > + tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], > + ctx->icr_ie_offset, 1); > } else { > generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); > } Need to exit the tb, like for ENABLE. r~