From: Jiangyifei via <qemu-devel@nongnu.org>
To: Richard Henderson <richard.henderson@linaro.org>,
Anup Patel <anup@brainfault.org>
Cc: Bin Meng <bin.meng@windriver.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"limingwang (A)" <limingwang@huawei.com>,
"KVM General" <kvm@vger.kernel.org>,
"libvir-list@redhat.com" <libvir-list@redhat.com>,
Anup Patel <anup.patel@wdc.com>,
QEMU Developers <qemu-devel@nongnu.org>,
"wanbo (G)" <wanbo13@huawei.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
"kvm-riscv@lists.infradead.org" <kvm-riscv@lists.infradead.org>,
"Wanghaibin (D)" <wanghaibin.wang@huawei.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
"Fanliang (EulerOS)" <fanliang@huawei.com>,
"Wubin (H)" <wu.wubin@huawei.com>
Subject: RE: [PATCH v2 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer
Date: Mon, 20 Dec 2021 13:02:01 +0000 [thread overview]
Message-ID: <229748f67a154a728f149b02e1f097f9@huawei.com> (raw)
In-Reply-To: <dec3147b-24bc-7e48-680b-a7423b0640f9@linaro.org>
> -----Original Message-----
> From: Richard Henderson [mailto:richard.henderson@linaro.org]
> Sent: Monday, December 13, 2021 11:20 PM
> To: Anup Patel <anup@brainfault.org>; Jiangyifei <jiangyifei@huawei.com>
> Cc: Bin Meng <bin.meng@windriver.com>; open list:RISC-V
> <qemu-riscv@nongnu.org>; limingwang (A) <limingwang@huawei.com>; KVM
> General <kvm@vger.kernel.org>; libvir-list@redhat.com; Anup Patel
> <anup.patel@wdc.com>; QEMU Developers <qemu-devel@nongnu.org>;
> wanbo (G) <wanbo13@huawei.com>; Palmer Dabbelt <palmer@dabbelt.com>;
> kvm-riscv@lists.infradead.org; Wanghaibin (D)
> <wanghaibin.wang@huawei.com>; Alistair Francis
> <Alistair.Francis@wdc.com>; Fanliang (EulerOS) <fanliang@huawei.com>;
> Wubin (H) <wu.wubin@huawei.com>
> Subject: Re: [PATCH v2 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer
>
> On 12/12/21 9:05 PM, Anup Patel wrote:
> >> + ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, state), ®);
> >> + if (ret) {
> >> + abort();
> >> + }
> >> + env->kvm_timer_state = reg;
> >
> > Please read the timer frequency here.
>
> Yep.
>
> >> +
> >> + env->kvm_timer_dirty = true;
> >> +}
> >> +
> >> +static void kvm_riscv_put_regs_timer(CPUState *cs) {
> >> + int ret;
> >> + uint64_t reg;
> >> + CPURISCVState *env = &RISCV_CPU(cs)->env;
> >> +
> >> + if (!env->kvm_timer_dirty) {
> >> + return;
> >> + }
> >
> > Over here, we should get the timer frequency and abort() with an error
> > message if it does not match env->kvm_timer_frequency
> >
> > For now, migration will not work between Hosts with different timer
> > frequency.
>
> You shouldn't have to do this every "put", only on migration, at which point you
> can actually signal a migration error rather than aborting directly.
>
>
> r~
Yes, it will be modified in the next series.
Yifei
next prev parent reply other threads:[~2021-12-20 17:20 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-10 10:07 [PATCH v2 00/12] Add riscv kvm accel support Yifei Jiang via
2021-12-10 10:07 ` [PATCH v2 01/12] update-linux-headers: Add asm-riscv/kvm.h Yifei Jiang via
2021-12-10 10:07 ` [PATCH v2 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang via
2021-12-10 10:07 ` [PATCH v2 03/12] target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang via
2021-12-13 4:15 ` Anup Patel
2021-12-10 10:07 ` [PATCH v2 04/12] target/riscv: Implement kvm_arch_get_registers Yifei Jiang via
2021-12-13 4:16 ` Anup Patel
2021-12-10 10:07 ` [PATCH v2 05/12] target/riscv: Implement kvm_arch_put_registers Yifei Jiang via
2021-12-13 4:17 ` Anup Patel
2021-12-10 10:07 ` [PATCH v2 06/12] target/riscv: Support start kernel directly by KVM Yifei Jiang via
2021-12-13 4:21 ` Anup Patel
2021-12-20 12:59 ` Jiangyifei via
2021-12-10 10:07 ` [PATCH v2 07/12] target/riscv: Support setting external interrupt " Yifei Jiang via
2021-12-13 4:32 ` Anup Patel
2021-12-20 13:01 ` Jiangyifei via
2021-12-10 10:07 ` [PATCH v2 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit Yifei Jiang via
2021-12-13 4:37 ` Anup Patel
2021-12-10 10:07 ` [PATCH v2 09/12] target/riscv: Add host cpu type Yifei Jiang via
2021-12-10 10:07 ` [PATCH v2 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer Yifei Jiang via
2021-12-13 5:05 ` Anup Patel
2021-12-13 15:19 ` Richard Henderson
2021-12-20 13:02 ` Jiangyifei via [this message]
2021-12-10 10:07 ` [PATCH v2 11/12] target/riscv: Implement virtual time adjusting with vm state changing Yifei Jiang via
2021-12-13 4:39 ` Anup Patel
2021-12-10 10:07 ` [PATCH v2 12/12] target/riscv: Support virtual time context synchronization Yifei Jiang via
2021-12-13 4:42 ` Anup Patel
2021-12-13 15:21 ` Richard Henderson
2021-12-20 13:02 ` Jiangyifei via
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