From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 549FCC4332F for ; Fri, 30 Sep 2022 15:02:14 +0000 (UTC) Received: from localhost ([::1]:57382 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeHWn-0000MZ-6O for qemu-devel@archiver.kernel.org; Fri, 30 Sep 2022 11:02:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52806) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeHUa-00072t-0G for qemu-devel@nongnu.org; Fri, 30 Sep 2022 10:59:56 -0400 Received: from 5.mo552.mail-out.ovh.net ([188.165.45.220]:42337) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeHUX-0004DH-V0 for qemu-devel@nongnu.org; Fri, 30 Sep 2022 10:59:55 -0400 Received: from mxplan5.mail.ovh.net (unknown [10.108.4.66]) by mo552.mail-out.ovh.net (Postfix) with ESMTPS id 4870F2BFD3; Fri, 30 Sep 2022 14:59:41 +0000 (UTC) Received: from kaod.org (37.59.142.100) by DAG4EX2.mxp5.local (172.16.2.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 30 Sep 2022 16:59:40 +0200 Authentication-Results: garm.ovh; auth=pass (GARM-100R003290681a6-2b22-418f-9b4b-2fc7677945f8, A23DC664A2347F08C02F66A015DE38D73296DB41) smtp.auth=clg@kaod.org X-OVh-ClientIp: 82.64.250.170 Message-ID: <229f555d-5f69-1c40-c65d-552a0ed8a39d@kaod.org> Date: Fri, 30 Sep 2022 16:59:35 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.0 Subject: Re: [PATCH 1/2] target/arm: Disable VFPv4-D32 when NEON is not available Content-Language: en-US To: Peter Maydell CC: , , Richard Henderson , Joel Stanley , Andrew Jeffery References: <20220928164719.655586-1-clg@kaod.org> <20220928164719.655586-2-clg@kaod.org> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [37.59.142.100] X-ClientProxiedBy: DAG3EX1.mxp5.local (172.16.2.21) To DAG4EX2.mxp5.local (172.16.2.32) X-Ovh-Tracer-GUID: bb5a9dfa-7ab8-4321-9f34-d55784dcb86f X-Ovh-Tracer-Id: 314407551175068454 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedvfedrfeehvddgkedvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhepkfffgggfuffvvehfhfgjtgfgihesthekredttdefjeenucfhrhhomhepveorughrihgtpgfnvggpifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucggtffrrghtthgvrhhnpeekteejtdelkeejvdevffduhfetteelieefgeefffeugffhfeekheffueefledujeenucfkpheptddrtddrtddrtddpfeejrdehledrudegvddruddttdenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhhouggvpehsmhhtphhouhhtpdhhvghlohepmhigphhlrghnhedrmhgrihhlrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdpnhgspghrtghpthhtohepuddprhgtphhtthhopegrnhgurhgvfiesrghjrdhiugdrrghupdfovfetjfhoshhtpehmohehhedv Received-SPF: pass client-ip=188.165.45.220; envelope-from=clg@kaod.org; helo=5.mo552.mail-out.ovh.net X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.583, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/29/22 13:44, Peter Maydell wrote: > On Wed, 28 Sept 2022 at 17:47, Cédric Le Goater wrote: >> >> As the Cortex A7 MPCore Technical reference says : >> >> "When FPU option is selected without NEON, the FPU is VFPv4-D16 and >> uses 16 double-precision registers. When the FPU is implemented with >> NEON, the FPU is VFPv4-D32 and uses 32 double-precision registers. >> This register bank is shared with NEON." >> >> Modify the mvfr0 register value of the cortex A7 to advertise only 16 >> registers when NEON is not available, and not 32 registers. >> >> Signed-off-by: Cédric Le Goater >> --- >> target/arm/cpu.c | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/target/arm/cpu.c b/target/arm/cpu.c >> index 7ec3281da9aa..01dc74c32add 100644 >> --- a/target/arm/cpu.c >> +++ b/target/arm/cpu.c >> @@ -1684,6 +1684,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) >> cpu->isar.id_isar6 = u; >> >> if (!arm_feature(env, ARM_FEATURE_M)) { >> + u = cpu->isar.mvfr0; >> + u = FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */ >> + cpu->isar.mvfr0 = u; >> + > > Architecturally, Neon implies that you must have 32 dp registers, > but not having Neon does not imply that you must only have 16. > In particular, the Cortex-A15 always implements VFPv4-D32 > whether Neon is enabled or not. > > If you want to be able to turn off D32 and restrict to 16 > registers, I think you need to add a separate property to > control that. Something like "vfp-d16" ? Thanks, C.