From: Richard Henderson <richard.henderson@linaro.org>
To: Sergey Matyukevich <geomatsi@gmail.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Subject: Re: [PATCH] target/riscv: set tval for triggered watchpoints
Date: Mon, 30 Jan 2023 09:10:51 -1000 [thread overview]
Message-ID: <22ab5f33-5ab7-7260-391f-375cd98a68ae@linaro.org> (raw)
In-Reply-To: <20230130100757.721372-1-geomatsi@gmail.com>
On 1/30/23 00:07, Sergey Matyukevich wrote:
> From: Sergey Matyukevich<sergey.matyukevich@syntacore.com>
>
> According to priviledged spec, if [sm]tval is written with a nonzero
> value when a breakpoint exception occurs, then [sm]tval will contain
> the faulting virtual address. Set tval to hit address when breakpoint
> exception is triggered by hardware watchpoint.
>
> Signed-off-by: Sergey Matyukevich<sergey.matyukevich@syntacore.com>
> ---
> target/riscv/cpu_helper.c | 3 +++
> target/riscv/debug.c | 1 +
> 2 files changed, 4 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2023-01-30 19:11 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-30 10:07 [PATCH] target/riscv: set tval for triggered watchpoints Sergey Matyukevich
2023-01-30 19:10 ` Richard Henderson [this message]
2023-01-31 0:19 ` Alistair Francis
2023-01-31 0:58 ` Alistair Francis
2023-01-31 1:52 ` Bin Meng
2023-01-31 7:58 ` Sergey Matyukevich
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