From: Paul Clarke <pc@us.ibm.com>
To: "Richard Henderson" <richard.henderson@linaro.org>,
"Alex Bennée" <alex.bennee@linaro.org>,
qemu-devel@nongnu.org
Cc: stefan.brankovic@rt-rk.com,
"qemu-ppc@nongnu.org" <qemu-ppc@nongnu.org>,
Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Subject: Re: Re: target/ppc: bug in optimised vsl/vsr implementation?
Date: Wed, 2 Oct 2019 14:55:02 -0500 [thread overview]
Message-ID: <22cc1b49-189d-95b6-ad83-e32ead2df7fe@us.ibm.com> (raw)
In-Reply-To: <5f80d547-3027-2315-bb98-221283b9df2f@linaro.org>
On 10/2/19 2:40 PM, Richard Henderson wrote:
> On 10/2/19 10:38 AM, Alex Bennée wrote:
>> Is the denbcdq instruction exposed in any standard float operations?
>> Once this is fixed it would be worth adding a testcase (either ppc64
>> specific or multiarch) so protect it from regression in the future.
>
> Not standard float operations -- this is binary coded decimal stuff.
> It would certainly be possible to write a ppc specific test case.
In comment #9 in the bug (https://bugs.launchpad.net/qemu/+bug/1841990/comments/9), I note that the issue was produced in running the test suite for the Power Vector Library project (https://github.com/open-power-sdk/pveclib), which makes productive use of dcbenq.
Maybe that could be adopted or adapted to suit?
PC
next prev parent reply other threads:[~2019-10-02 19:57 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-26 18:04 target/ppc: bug in optimised vsl/vsr implementation? Mark Cave-Ayland
2019-09-28 17:45 ` Aleksandar Markovic
2019-09-28 22:17 ` Aleksandar Markovic
2019-09-30 14:34 ` Paul Clarke
2019-09-30 14:53 ` Aleksandar Markovic
2019-09-30 14:37 ` Aleksandar Markovic
2019-10-01 18:24 ` Mark Cave-Ayland
2019-10-02 14:08 ` Stefan Brankovic
2019-10-03 11:11 ` Stefan Brankovic
2019-10-02 17:38 ` Alex Bennée
2019-10-02 19:40 ` Richard Henderson
2019-10-02 19:55 ` Paul Clarke [this message]
2019-10-04 19:32 ` Aleksandar Markovic
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