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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4389046226asm186737945e9.31.2025.01.21.11.05.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Jan 2025 11:05:35 -0800 (PST) Message-ID: <22d7e41b-925c-4ea8-819f-80936e5c8e71@linaro.org> Date: Tue, 21 Jan 2025 20:05:34 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] target/riscv/debug.c: use wp size = 4 for 32-bit CPUs To: Daniel Henrique Barboza , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, richard.henderson@linaro.org References: <20250120204910.1317013-1-dbarboza@ventanamicro.com> <20250120204910.1317013-2-dbarboza@ventanamicro.com> <9b2114bb-ed61-42bc-a5fe-f28a6a5319dc@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 21/1/25 19:47, Daniel Henrique Barboza wrote: > > > On 1/21/25 2:40 PM, Philippe Mathieu-Daudé wrote: >> On 20/1/25 21:49, Daniel Henrique Barboza wrote: >>> The mcontrol select bit (19) is always zero, meaning our triggers will >>> always match virtual addresses. In this condition, if the user does not >>> specify a size for the trigger, the access size defaults to XLEN. >>> >>> At this moment we're using def_size = 8 regardless of CPU XLEN. Use >>> def_size = 4 in case we're running 32 bits. >>> >>> Fixes: 95799e36c1 ("target/riscv: Add initial support for the Sdtrig >>> extension") >>> Signed-off-by: Daniel Henrique Barboza >>> --- >>>   target/riscv/debug.c | 6 ++++-- >>>   1 file changed, 4 insertions(+), 2 deletions(-) >>> @@ -501,7 +501,9 @@ static void type2_breakpoint_insert(CPURISCVState >>> *env, target_ulong index) >>>               cpu_watchpoint_insert(cs, addr, size, flags, >>>                                     &env->cpu_watchpoint[index]); >>>           } else { >>> -            cpu_watchpoint_insert(cs, addr, 8, flags, >>> +            def_size = riscv_cpu_mxl(env) == MXL_RV64 ? 8 : 4; >> >> riscv_cpu_mxl() seems bugprone w.r.t. MXL_RV128, better could be >> some riscv_cpu_mxl_wordsize() helper like riscv_cpu_mxl_bits() >> (or better named). > > This existing pattern is benign since we don't have a functional RV128 and > is safe seems to interpret RV64 == RV128. > > However, if/when RV128 becomes a thing, we'll spare a moderate amount of > agony 😱 > if we choose to have a little suffering right now. I'll take a note > about it > and perhaps a refactor might be in order. > > > Thanks, > > Daniel