From: liweiwei <liweiwei@iscas.ac.cn>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, zhiwei_liu@linux.alibaba.com
Subject: Re: [PATCH 4/4] target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig
Date: Sat, 25 Feb 2023 14:44:34 +0800 [thread overview]
Message-ID: <22e8a263-52db-8538-c71e-fcfb9cfef93b@iscas.ac.cn> (raw)
In-Reply-To: <20230224174520.92490-5-dbarboza@ventanamicro.com>
On 2023/2/25 01:45, Daniel Henrique Barboza wrote:
> Retrieving the CPU pointer using env_archcpu() just to access cpu->cfg
> can be avoided by using riscv_cpu_cfg().
>
> Suggested-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Weiwei Li
> ---
> target/riscv/csr.c | 32 +++++++++-----------------------
> 1 file changed, 9 insertions(+), 23 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 53f1a331f9..ffa2d7b606 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -213,9 +213,7 @@ static RISCVException any32(CPURISCVState *env, int csrno)
>
> static int aia_any(CPURISCVState *env, int csrno)
> {
> - RISCVCPU *cpu = env_archcpu(env);
> -
> - if (!cpu->cfg.ext_smaia) {
> + if (!riscv_cpu_cfg(env)->ext_smaia) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> @@ -224,9 +222,7 @@ static int aia_any(CPURISCVState *env, int csrno)
>
> static int aia_any32(CPURISCVState *env, int csrno)
> {
> - RISCVCPU *cpu = env_archcpu(env);
> -
> - if (!cpu->cfg.ext_smaia) {
> + if (!riscv_cpu_cfg(env)->ext_smaia) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> @@ -253,9 +249,7 @@ static int smode32(CPURISCVState *env, int csrno)
>
> static int aia_smode(CPURISCVState *env, int csrno)
> {
> - RISCVCPU *cpu = env_archcpu(env);
> -
> - if (!cpu->cfg.ext_ssaia) {
> + if (!riscv_cpu_cfg(env)->ext_ssaia) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> @@ -264,9 +258,7 @@ static int aia_smode(CPURISCVState *env, int csrno)
>
> static int aia_smode32(CPURISCVState *env, int csrno)
> {
> - RISCVCPU *cpu = env_archcpu(env);
> -
> - if (!cpu->cfg.ext_ssaia) {
> + if (!riscv_cpu_cfg(env)->ext_ssaia) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> @@ -380,9 +372,7 @@ static RISCVException pointer_masking(CPURISCVState *env, int csrno)
>
> static int aia_hmode(CPURISCVState *env, int csrno)
> {
> - RISCVCPU *cpu = env_archcpu(env);
> -
> - if (!cpu->cfg.ext_ssaia) {
> + if (!riscv_cpu_cfg(env)->ext_ssaia) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> @@ -391,9 +381,7 @@ static int aia_hmode(CPURISCVState *env, int csrno)
>
> static int aia_hmode32(CPURISCVState *env, int csrno)
> {
> - RISCVCPU *cpu = env_archcpu(env);
> -
> - if (!cpu->cfg.ext_ssaia) {
> + if (!riscv_cpu_cfg(env)->ext_ssaia) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> @@ -430,9 +418,7 @@ static RISCVException debug(CPURISCVState *env, int csrno)
>
> static RISCVException seed(CPURISCVState *env, int csrno)
> {
> - RISCVCPU *cpu = env_archcpu(env);
> -
> - if (!cpu->cfg.ext_zkr) {
> + if (!riscv_cpu_cfg(env)->ext_zkr) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> @@ -555,7 +541,7 @@ static RISCVException read_vl(CPURISCVState *env, int csrno,
>
> static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
> {
> - *val = env_archcpu(env)->cfg.vlen >> 3;
> + *val = riscv_cpu_cfg(env)->vlen >> 3;
> return RISCV_EXCP_NONE;
> }
>
> @@ -610,7 +596,7 @@ static RISCVException write_vstart(CPURISCVState *env, int csrno,
> * The vstart CSR is defined to have only enough writable bits
> * to hold the largest element index, i.e. lg2(VLEN) bits.
> */
> - env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen));
> + env->vstart = val & ~(~0ULL << ctzl(riscv_cpu_cfg(env)->vlen));
> return RISCV_EXCP_NONE;
> }
>
next prev parent reply other threads:[~2023-02-25 6:45 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-24 17:45 [PATCH 0/4] RISCVCPUConfig related cleanups Daniel Henrique Barboza
2023-02-24 17:45 ` [PATCH 1/4] target/riscv/csr.c: use env_archcpu() in ctr() Daniel Henrique Barboza
2023-02-25 6:40 ` liweiwei
2023-02-24 17:45 ` [PATCH 2/4] target/riscv/csr.c: simplify mctr() Daniel Henrique Barboza
2023-02-25 6:42 ` liweiwei
2023-02-24 17:45 ` [PATCH 3/4] target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers Daniel Henrique Barboza
2023-02-25 6:43 ` liweiwei
2023-02-24 17:45 ` [PATCH 4/4] target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig Daniel Henrique Barboza
2023-02-25 6:44 ` liweiwei [this message]
2023-02-24 21:34 ` [PATCH 0/4] RISCVCPUConfig related cleanups Richard Henderson
2023-02-24 21:36 ` Richard Henderson
2023-02-25 6:47 ` liweiwei
2023-02-26 17:39 ` Daniel Henrique Barboza
2023-03-02 2:07 ` Palmer Dabbelt
2023-03-02 2:24 ` Bin Meng
2023-03-02 8:10 ` Daniel Henrique Barboza
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