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From: Richard Henderson <richard.henderson@linaro.org>
To: David Hildenbrand <david@redhat.com>, qemu-devel@nongnu.org
Cc: qemu-s390x@nongnu.org, Cornelia Huck <cohuck@redhat.com>,
	Thomas Huth <thuth@redhat.com>
Subject: Re: [PATCH v5 1/2] target/s390x: Implement the MVPG condition-code-option bit
Date: Thu, 11 Mar 2021 11:26:06 -0600	[thread overview]
Message-ID: <232bc238-381f-5651-d0e5-e057e0a73b14@linaro.org> (raw)
In-Reply-To: <e9c74b31-28c9-6757-567e-a6d14a9a5b7e@redhat.com>

On 3/11/21 11:12 AM, David Hildenbrand wrote:
> Without an access key in GR0, we're using the PSW key - which should always 
> work, no?
> 
> What am I missing?

Nothing.  Insufficiently close reading on my part.


r~


  reply	other threads:[~2021-03-11 17:34 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-11 16:17 [PATCH v5 0/2] target/s390x: Implement the MVPG condition-code-option bit David Hildenbrand
2021-03-11 16:17 ` [PATCH v5 1/2] " David Hildenbrand
2021-03-11 17:02   ` Richard Henderson
2021-03-11 17:12     ` David Hildenbrand
2021-03-11 17:26       ` Richard Henderson [this message]
2021-03-11 17:52   ` Richard Henderson
2021-03-11 18:16     ` David Hildenbrand
2021-03-11 18:24       ` Richard Henderson
2021-03-11 16:17 ` [PATCH v5 2/2] target/s390x: Store r1/r2 for page-translation exceptions during MVPG David Hildenbrand
2021-03-11 16:26   ` David Hildenbrand

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