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[176.184.47.225]) by smtp.gmail.com with ESMTPSA id x14-20020a5d490e000000b0031423a8f4f7sm199201wrq.56.2023.07.10.12.21.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 Jul 2023 12:21:26 -0700 (PDT) Message-ID: <234d7b82-e34e-53db-34de-c7cfe05ab204@linaro.org> Date: Mon, 10 Jul 2023 21:21:24 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH] target/mips: Rework cp0_timer with clock API Content-Language: en-US To: Jiaxun Yang , qemu-devel@nongnu.org Cc: chenhuacai@kernel.org References: <20230521110037.90049-1-jiaxun.yang@flygoat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230521110037.90049-1-jiaxun.yang@flygoat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.101, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 21/5/23 13:00, Jiaxun Yang wrote: > Previous implementation of MIPS cp0_timer computes a > cp0_count_ns based on input clock. However rounding > error of cp0_count_ns can affect precision of cp0_timer. > > Using clock API and a divider for cp0_timer, so we can > use clock_ns_to_ticks/clock_ns_to_ticks to avoid rounding > issue. > > Also workaround the situation that in such handler flow: > > count = read_c0_count() > write_c0_compare(count) > > If timer had not progressed when compare was written, the > interrupt would trigger again. > > Signed-off-by: Jiaxun Yang > --- > This seems fixed MTTCG booting issue on malta 5kEc with SMP. > I'm going to do more test and see if we can enable MTTCG for > mips64el. > --- > target/mips/cpu.c | 8 +++++--- > target/mips/cpu.h | 3 ++- > target/mips/sysemu/cp0_timer.c | 35 ++++++++++++++++++---------------- > 3 files changed, 26 insertions(+), 20 deletions(-) Thanks, queued to mips-next.