From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <Alistair.Francis@wdc.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Cc: "alistair23@gmail.com" <alistair23@gmail.com>
Subject: Re: [Qemu-devel] [RFC v1 15/23] riscv: tcg-target: Add branch and jump instructions
Date: Fri, 16 Nov 2018 10:14:28 +0100 [thread overview]
Message-ID: <23831afc-0ebf-5802-e8e2-6ce48dd340f9@linaro.org> (raw)
In-Reply-To: <f1a7d2617c26c1745fafe13bbe3bc3b042c14217.1542321076.git.alistair.francis@wdc.com>
On 11/15/18 11:36 PM, Alistair Francis wrote:
> +static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
> + TCGReg arg2, TCGLabel *l)
> +{
> + RISCVInsn op = tcg_brcond_to_riscv[cond].op;
> + bool swap = tcg_brcond_to_riscv[cond].swap;
> +
> + tcg_out_opc_branch(s, op, swap ? arg2 : arg1, swap ? arg1 : arg2, 0);
You might want to tcg_debug_assert(op != 0) here.
> + if (l->has_value) {
> + reloc_sbimm12(s->code_ptr - 1, l->u.value_ptr);
I'm concerned about the conditional branch range. +-4K isn't much to work
with. The minimum we have for other hosts is +-32K.
We have two options: (1) greatly reduce the max size of the TB for this host;
(2) be prepared to emit a 2 insn sequence: conditional branch across
unconditional branch, with forward branches that turn out to be small patched
with a nop.
FWIW, the first case would be done via modification of tcg_op_buf_full. You
might have to go as low as 500 opcodes, I'm not sure.
> +static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target)
> +{
> + ptrdiff_t offset = tcg_pcrel_diff(s, target);
> + tcg_debug_assert(offset == sextract64(offset, 0, 26));
> + tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, offset);
> +}
> +
> +static inline void tcg_out_goto_long(TCGContext *s, tcg_insn_unit *target)
> +{
> + ptrdiff_t offset = tcg_pcrel_diff(s, target);
> +
> + if (offset == sextract64(offset, 0, 26)) {
> + tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, offset);
> + } else {
> + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, (intptr_t)target);
> + tcg_out_opc_jump(s, OPC_JAL, TCG_REG_TMP0, 0);
> + }
> +}
How are these to be used? I guess I'll find out...
> +static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail)
> +{
> + TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA;
> + ptrdiff_t offset = tcg_pcrel_diff(s, arg);
> + if (offset == sextract32(offset, 1, 20) << 1) {
sextract64.
> + /* short jump: -2097150 to 2097152 */
> + tcg_out_opc_jump(s, OPC_JAL, link, offset);
> + } else if (TCG_TARGET_REG_BITS == 32 ||
> + offset == sextract32(offset, 1, 31) << 1) {
sextract64.
> + /* long jump: -2147483646 to 2147483648 */
> + tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0);
> + tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0);
> + reloc_call(s->code_ptr - 2, arg);
> + } else if (TCG_TARGET_REG_BITS == 64) {
> + /* far jump: 64-bit */
> + tcg_target_long imm = sextract32((tcg_target_long)arg, 0, 12);
> + tcg_target_long base = (tcg_target_long)arg - imm;
> + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, base);
> + tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm);
r~
next prev parent reply other threads:[~2018-11-16 9:14 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-15 22:33 [Qemu-devel] [RFC v1 00/23] Add RISC-V TCG backend support Alistair Francis
2018-11-15 22:34 ` [Qemu-devel] [RFC v1 01/23] elf.h: Add the RISCV ELF magic numbers Alistair Francis
2018-11-16 7:46 ` Richard Henderson
2018-11-15 22:34 ` [Qemu-devel] [RFC v1 02/23] linux-user: Add host dependency for RISC-V 32-bit Alistair Francis
2018-11-16 7:46 ` Richard Henderson
2018-11-16 7:47 ` Richard Henderson
2018-11-15 22:34 ` [Qemu-devel] [RFC v1 03/23] linux-user: Add host dependency for RISC-V 64-bit Alistair Francis
2018-11-16 7:57 ` Richard Henderson
2018-11-15 22:34 ` [Qemu-devel] [RFC v1 04/23] exec: Add RISC-V GCC poison macro Alistair Francis
2018-11-16 7:47 ` Richard Henderson
2018-11-15 22:34 ` [Qemu-devel] [RFC v1 05/23] riscv: Add the tcg-target header file Alistair Francis
2018-11-16 7:57 ` Richard Henderson
2018-11-16 17:20 ` Richard Henderson
2018-11-15 22:34 ` [Qemu-devel] [RFC v1 06/23] riscv: Add the tcg target registers Alistair Francis
2018-11-16 7:58 ` Richard Henderson
2018-11-15 22:34 ` [Qemu-devel] [RFC v1 07/23] riscv: tcg-target: Regiser the JIT Alistair Francis
2018-11-16 7:59 ` Richard Henderson
2018-11-15 22:35 ` [Qemu-devel] [RFC v1 08/23] riscv: tcg-target: Add support for the constraints Alistair Francis
2018-11-16 8:13 ` Richard Henderson
2018-11-15 22:35 ` [Qemu-devel] [RFC v1 09/23] riscv: tcg-target: Add the immediate encoders Alistair Francis
2018-11-16 8:26 ` Richard Henderson
2018-11-15 22:35 ` [Qemu-devel] [RFC v1 10/23] riscv: tcg-target: Add the instruction emitters Alistair Francis
2018-11-16 8:27 ` Richard Henderson
2018-11-15 22:35 ` [Qemu-devel] [RFC v1 11/23] riscv: tcg-target: Add the relocation functions Alistair Francis
2018-11-16 8:33 ` Richard Henderson
2018-11-21 1:15 ` Alistair Francis
2018-11-21 7:25 ` Richard Henderson
2018-11-21 15:53 ` Palmer Dabbelt
2018-11-21 17:01 ` Richard Henderson
2018-11-15 22:35 ` [Qemu-devel] [RFC v1 12/23] riscv: tcg-target: Add the mov and movi instruction Alistair Francis
2018-11-16 8:55 ` Richard Henderson
2018-11-15 22:35 ` [Qemu-devel] [RFC v1 13/23] riscv: tcg-target: Add the extract instructions Alistair Francis
2018-11-16 8:56 ` Richard Henderson
2018-11-15 22:36 ` [Qemu-devel] [RFC v1 14/23] riscv: tcg-target: Add the out load and store instructions Alistair Francis
2018-11-16 8:59 ` Richard Henderson
2018-11-15 22:36 ` [Qemu-devel] [RFC v1 15/23] riscv: tcg-target: Add branch and jump instructions Alistair Francis
2018-11-16 9:14 ` Richard Henderson [this message]
2018-11-20 23:49 ` Alistair Francis
2018-11-21 7:40 ` Richard Henderson
2018-11-26 22:58 ` Alistair Francis
2018-11-15 22:36 ` [Qemu-devel] [RFC v1 16/23] riscv: tcg-target: Add slowpath load and store instructions Alistair Francis
2018-11-16 9:24 ` Richard Henderson
2018-11-21 0:18 ` Alistair Francis
2018-11-21 7:43 ` Richard Henderson
2018-11-15 22:36 ` [Qemu-devel] [RFC v1 17/23] riscv: tcg-target: Add direct " Alistair Francis
2018-11-16 17:10 ` Richard Henderson
2018-11-19 23:06 ` Alistair Francis
2018-11-20 6:57 ` Richard Henderson
2018-11-15 22:36 ` [Qemu-devel] [RFC v1 18/23] riscv: tcg-target: Add the out op decoder Alistair Francis
2018-11-16 17:22 ` Richard Henderson
2018-11-15 22:36 ` [Qemu-devel] [RFC v1 19/23] riscv: tcg-target: Add the prologue generation Alistair Francis
2018-11-16 17:25 ` Richard Henderson
2018-11-15 22:36 ` [Qemu-devel] [RFC v1 20/23] riscv: tcg-target: Add the target init code Alistair Francis
2018-11-16 17:26 ` Richard Henderson
2018-11-19 23:04 ` Alistair Francis
2018-11-20 6:55 ` Richard Henderson
2018-11-20 23:22 ` Alistair Francis
2018-11-15 22:37 ` [Qemu-devel] [RFC v1 21/23] tcg: Add RISC-V cpu signal handler Alistair Francis
2018-11-16 17:27 ` Richard Henderson
2018-11-16 17:29 ` Richard Henderson
2018-11-15 22:37 ` [Qemu-devel] [RFC v1 22/23] dias: Add RISC-V support Alistair Francis
2018-11-16 17:29 ` Richard Henderson
2018-11-15 22:37 ` [Qemu-devel] [RFC v1 23/23] configure: Add support for building RISC-V host Alistair Francis
2018-11-16 17:30 ` Richard Henderson
2018-11-16 8:31 ` [Qemu-devel] [RFC v1 00/23] Add RISC-V TCG backend support no-reply
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