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([2a01:e0a:280:24f0:9db0:474c:ff43:9f5c]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3d85f80d8casm519459f8f.54.2025.08.31.23.59.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 31 Aug 2025 23:59:54 -0700 (PDT) Message-ID: <238387ee-055e-40c2-a889-66cb320e26c8@redhat.com> Date: Mon, 1 Sep 2025 08:59:53 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] fix: Fix build error with CONFIG_POWERNV disabled To: Aditya Gupta , Nicholas Piggin , Harsh Prateek Bora , Chinmay Rath Cc: Michael Tokarev , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth References: <20250820122516.949766-2-adityag@linux.ibm.com> From: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= Content-Language: en-US, fr Autocrypt: addr=clg@redhat.com; keydata= xsFNBFu8o3UBEADP+oJVJaWm5vzZa/iLgpBAuzxSmNYhURZH+guITvSySk30YWfLYGBWQgeo 8NzNXBY3cH7JX3/a0jzmhDc0U61qFxVgrPqs1PQOjp7yRSFuDAnjtRqNvWkvlnRWLFq4+U5t yzYe4SFMjFb6Oc0xkQmaK2flmiJNnnxPttYwKBPd98WfXMmjwAv7QfwW+OL3VlTPADgzkcqj 53bfZ4VblAQrq6Ctbtu7JuUGAxSIL3XqeQlAwwLTfFGrmpY7MroE7n9Rl+hy/kuIrb/TO8n0 ZxYXvvhT7OmRKvbYuc5Jze6o7op/bJHlufY+AquYQ4dPxjPPVUT/DLiUYJ3oVBWFYNbzfOrV RxEwNuRbycttMiZWxgflsQoHF06q/2l4ttS3zsV4TDZudMq0TbCH/uJFPFsbHUN91qwwaN/+ gy1j7o6aWMz+Ib3O9dK2M/j/O/Ube95mdCqN4N/uSnDlca3YDEWrV9jO1mUS/ndOkjxa34ia 70FjwiSQAsyIwqbRO3CGmiOJqDa9qNvd2TJgAaS2WCw/TlBALjVQ7AyoPEoBPj31K74Wc4GS Rm+FSch32ei61yFu6ACdZ12i5Edt+To+hkElzjt6db/UgRUeKfzlMB7PodK7o8NBD8outJGS tsL2GRX24QvvBuusJdMiLGpNz3uqyqwzC5w0Fd34E6G94806fwARAQABzSJDw6lkcmljIExl IEdvYXRlciA8Y2xnQHJlZGhhdC5jb20+wsGRBBMBCAA7FiEEoPZlSPBIlev+awtgUaNDx8/7 7KEFAmTLlVECGwMFCwkIBwICIgIGFQoJCAsCBBYCAwECHgcCF4AACgkQUaNDx8/77KG0eg// S0zIzTcxkrwJ/9XgdcvVTnXLVF9V4/tZPfB7sCp8rpDCEseU6O0TkOVFoGWM39sEMiQBSvyY lHrP7p7E/JYQNNLh441MfaX8RJ5Ul3btluLapm8oHp/vbHKV2IhLcpNCfAqaQKdfk8yazYhh EdxTBlzxPcu+78uE5fF4wusmtutK0JG0sAgq0mHFZX7qKG6LIbdLdaQalZ8CCFMKUhLptW71 xe+aNrn7hScBoOj2kTDRgf9CE7svmjGToJzUxgeh9mIkxAxTu7XU+8lmL28j2L5uNuDOq9vl hM30OT+pfHmyPLtLK8+GXfFDxjea5hZLF+2yolE/ATQFt9AmOmXC+YayrcO2ZvdnKExZS1o8 VUKpZgRnkwMUUReaF/mTauRQGLuS4lDcI4DrARPyLGNbvYlpmJWnGRWCDguQ/LBPpbG7djoy k3NlvoeA757c4DgCzggViqLm0Bae320qEc6z9o0X0ePqSU2f7vcuWN49Uhox5kM5L86DzjEQ RHXndoJkeL8LmHx8DM+kx4aZt0zVfCHwmKTkSTQoAQakLpLte7tWXIio9ZKhUGPv/eHxXEoS 0rOOAZ6np1U/xNR82QbF9qr9TrTVI3GtVe7Vxmff+qoSAxJiZQCo5kt0YlWwti2fFI4xvkOi V7lyhOA3+/3oRKpZYQ86Frlo61HU3r6d9wzOwU0EW7yjdQEQALyDNNMw/08/fsyWEWjfqVhW pOOrX2h+z4q0lOHkjxi/FRIRLfXeZjFfNQNLSoL8j1y2rQOs1j1g+NV3K5hrZYYcMs0xhmrZ KXAHjjDx7FW3sG3jcGjFW5Xk4olTrZwFsZVUcP8XZlArLmkAX3UyrrXEWPSBJCXxDIW1hzwp bV/nVbo/K9XBptT/wPd+RPiOTIIRptjypGY+S23HYBDND3mtfTz/uY0Jytaio9GETj+fFis6 TxFjjbZNUxKpwftu/4RimZ7qL+uM1rG1lLWc9SPtFxRQ8uLvLOUFB1AqHixBcx7LIXSKZEFU CSLB2AE4wXQkJbApye48qnZ09zc929df5gU6hjgqV9Gk1rIfHxvTsYltA1jWalySEScmr0iS YBZjw8Nbd7SxeomAxzBv2l1Fk8fPzR7M616dtb3Z3HLjyvwAwxtfGD7VnvINPbzyibbe9c6g LxYCr23c2Ry0UfFXh6UKD83d5ybqnXrEJ5n/t1+TLGCYGzF2erVYGkQrReJe8Mld3iGVldB7 JhuAU1+d88NS3aBpNF6TbGXqlXGF6Yua6n1cOY2Yb4lO/mDKgjXd3aviqlwVlodC8AwI0Sdu jWryzL5/AGEU2sIDQCHuv1QgzmKwhE58d475KdVX/3Vt5I9kTXpvEpfW18TjlFkdHGESM/Jx IqVsqvhAJkalABEBAAHCwV8EGAECAAkFAlu8o3UCGwwACgkQUaNDx8/77KEhwg//WqVopd5k 8hQb9VVdk6RQOCTfo6wHhEqgjbXQGlaxKHoXywEQBi8eULbeMQf5l4+tHJWBxswQ93IHBQjK yKyNr4FXseUI5O20XVNYDJZUrhA4yn0e/Af0IX25d94HXQ5sMTWr1qlSK6Zu79lbH3R57w9j hQm9emQEp785ui3A5U2Lqp6nWYWXz0eUZ0Tad2zC71Gg9VazU9MXyWn749s0nXbVLcLS0yop s302Gf3ZmtgfXTX/W+M25hiVRRKCH88yr6it+OMJBUndQVAA/fE9hYom6t/zqA248j0QAV/p LHH3hSirE1mv+7jpQnhMvatrwUpeXrOiEw1nHzWCqOJUZ4SY+HmGFW0YirWV2mYKoaGO2YBU wYF7O9TI3GEEgRMBIRT98fHa0NPwtlTktVISl73LpgVscdW8yg9Gc82oe8FzU1uHjU8b10lU XOMHpqDDEV9//r4ZhkKZ9C4O+YZcTFu+mvAY3GlqivBNkmYsHYSlFsbxc37E1HpTEaSWsGfA HQoPn9qrDJgsgcbBVc1gkUT6hnxShKPp4PlsZVMNjvPAnr5TEBgHkk54HQRhhwcYv1T2QumQ izDiU6iOrUzBThaMhZO3i927SG2DwWDVzZltKrCMD1aMPvb3NU8FOYRhNmIFR3fcalYr+9gD uVKe8BVz4atMOoktmt0GWTOC8P4= In-Reply-To: <20250820122516.949766-2-adityag@linux.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/20/25 14:25, Aditya Gupta wrote: > Currently when CONFIG_POWERNV is not enabled, the build fails, such as > with --without-default-devices: > > $ ./configure --without-default-devices > $ make > > [281/283] Linking target qemu-system-ppc64 > FAILED: qemu-system-ppc64 > cc -m64 @qemu-system-ppc64.rsp > /usr/bin/ld: libqemu-ppc64-softmmu.a.p/target_ppc_misc_helper.c.o: in function `helper_load_sprd': > .../target/ppc/misc_helper.c:335:(.text+0xcdc): undefined reference to `pnv_chip_find_core' > /usr/bin/ld: libqemu-ppc64-softmmu.a.p/target_ppc_misc_helper.c.o: in function `helper_store_sprd': > .../target/ppc/misc_helper.c:375:(.text+0xdf4): undefined reference to `pnv_chip_find_core' > collect2: error: ld returned 1 exit status > ... > > This is since target/ppc/misc_helper.c references PowerNV specific > 'pnv_chip_find_core' call. > > Split the PowerNV specific SPRD code out of the generic PowerPC code, by > moving the SPRD code to pnv.c > > Fixes: 9808ce6d5cb ("target/ppc: Big-core scratch register fix") > Cc: Philippe Mathieu-Daudé > Reported-by: Thomas Huth > Suggested-by: Cédric Le Goater > Signed-off-by: Aditya Gupta Acked-by: Cédric Le Goater Thanks, C. > --- > Note that while moving the code, the 'target_ulong' type for sprc has been > modified to 'uint64_t'. > > Based on the discussion happened on [1]. > Requires patch 1 and patch 2 of [1] to be applied, to fix the build. > > [1]: https://lore.kernel.org/qemu-devel/20250526112346.48744-1-philmd@linaro.org/ > --- > --- > hw/ppc/pnv.c | 86 ++++++++++++++++++++++++++++++++++++++++ > target/ppc/cpu.h | 4 ++ > target/ppc/misc_helper.c | 59 +++------------------------ > 3 files changed, 96 insertions(+), 53 deletions(-) > > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index d84c9067edb3..9c74f46091a7 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -21,6 +21,7 @@ > > #include "qemu/osdep.h" > #include "qemu/datadir.h" > +#include "qemu/log.h" > #include "qemu/units.h" > #include "qemu/cutils.h" > #include "qapi/error.h" > @@ -1794,12 +1795,83 @@ static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) > } > } > > +static uint64_t pnv_handle_sprd_load(CPUPPCState *env) > +{ > + PowerPCCPU *cpu = env_archcpu(env); > + PnvCore *pc = pnv_cpu_state(cpu)->pnv_core; > + uint64_t sprc = env->spr[SPR_POWER_SPRC]; > + > + if (pc->big_core) { > + pc = pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x1); > + } > + > + switch (sprc & 0x3e0) { > + case 0: /* SCRATCH0-3 */ > + case 1: /* SCRATCH4-7 */ > + return pc->scratch[(sprc >> 3) & 0x7]; > + > + case 0x1e0: /* core thread state */ > + if (env->excp_model == POWERPC_EXCP_POWER9) { > + /* > + * Only implement for POWER9 because skiboot uses it to check > + * big-core mode. Other bits are unimplemented so we would > + * prefer to get unimplemented message on POWER10 if it were > + * used anywhere. > + */ > + if (pc->big_core) { > + return PPC_BIT(63); > + } else { > + return 0; > + } > + } > + /* fallthru */ > + > + default: > + qemu_log_mask(LOG_UNIMP, "mfSPRD: Unimplemented SPRC:0x" > + TARGET_FMT_lx"\n", sprc); > + break; > + } > + return 0; > +} > + > +static void pnv_handle_sprd_store(CPUPPCState *env, uint64_t val) > +{ > + PowerPCCPU *cpu = env_archcpu(env); > + uint64_t sprc = env->spr[SPR_POWER_SPRC]; > + PnvCore *pc = pnv_cpu_state(cpu)->pnv_core; > + int nr; > + > + if (pc->big_core) { > + pc = pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x1); > + } > + > + switch (sprc & 0x3e0) { > + case 0: /* SCRATCH0-3 */ > + case 1: /* SCRATCH4-7 */ > + /* > + * Log stores to SCRATCH, because some firmware uses these for > + * debugging and logging, but they would normally be read by the BMC, > + * which is not implemented in QEMU yet. This gives a way to get at the > + * information. Could also dump these upon checkstop. > + */ > + nr = (sprc >> 3) & 0x7; > + pc->scratch[nr] = val; > + break; > + default: > + qemu_log_mask(LOG_UNIMP, "mtSPRD: Unimplemented SPRC:0x" > + TARGET_FMT_lx"\n", sprc); > + break; > + } > +} > + > static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) > { > PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); > Pnv9Chip *chip9 = PNV9_CHIP(dev); > PnvChip *chip = PNV_CHIP(dev); > Pnv9Psi *psi9 = &chip9->psi; > + PowerPCCPU *cpu; > + PowerPCCPUClass *cpu_class; > Error *local_err = NULL; > int i; > > @@ -1827,6 +1899,12 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) > return; > } > > + /* Set handlers for Special registers, such as SPRD */ > + cpu = chip->cores[0]->threads[0]; > + cpu_class = POWERPC_CPU_GET_CLASS(cpu); > + cpu_class->load_sprd = pnv_handle_sprd_load; > + cpu_class->store_sprd = pnv_handle_sprd_store; > + > /* XIVE interrupt controller (POWER9) */ > object_property_set_int(OBJECT(&chip9->xive), "ic-bar", > PNV9_XIVE_IC_BASE(chip), &error_fatal); > @@ -2078,6 +2156,8 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) > PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); > PnvChip *chip = PNV_CHIP(dev); > Pnv10Chip *chip10 = PNV10_CHIP(dev); > + PowerPCCPU *cpu; > + PowerPCCPUClass *cpu_class; > Error *local_err = NULL; > int i; > > @@ -2105,6 +2185,12 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) > return; > } > > + /* Set handlers for Special registers, such as SPRD */ > + cpu = chip->cores[0]->threads[0]; > + cpu_class = POWERPC_CPU_GET_CLASS(cpu); > + cpu_class->load_sprd = pnv_handle_sprd_load; > + cpu_class->store_sprd = pnv_handle_sprd_store; > + > /* XIVE2 interrupt controller (POWER10) */ > object_property_set_int(OBJECT(&chip10->xive), "ic-bar", > PNV10_XIVE2_IC_BASE(chip), &error_fatal); > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index 6b90543811f0..0e26e4343de7 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -1522,6 +1522,10 @@ struct PowerPCCPUClass { > void (*init_proc)(CPUPPCState *env); > int (*check_pow)(CPUPPCState *env); > int (*check_attn)(CPUPPCState *env); > + > + /* Handlers to be set by the machine initialising the chips */ > + uint64_t (*load_sprd)(CPUPPCState *env); > + void (*store_sprd)(CPUPPCState *env, uint64_t val); > }; > > static inline bool ppc_cpu_core_single_threaded(CPUState *cs) > diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c > index e7d94625185c..0e625cbb704d 100644 > --- a/target/ppc/misc_helper.c > +++ b/target/ppc/misc_helper.c > @@ -328,69 +328,22 @@ target_ulong helper_load_sprd(CPUPPCState *env) > * accessed by powernv machines. > */ > PowerPCCPU *cpu = env_archcpu(env); > - PnvCore *pc = pnv_cpu_state(cpu)->pnv_core; > - target_ulong sprc = env->spr[SPR_POWER_SPRC]; > + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); > > - if (pc->big_core) { > - pc = pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x1); > + if (pcc->load_sprd) { > + return pcc->load_sprd(env); > } > > - switch (sprc & 0x3e0) { > - case 0: /* SCRATCH0-3 */ > - case 1: /* SCRATCH4-7 */ > - return pc->scratch[(sprc >> 3) & 0x7]; > - > - case 0x1e0: /* core thread state */ > - if (env->excp_model == POWERPC_EXCP_POWER9) { > - /* > - * Only implement for POWER9 because skiboot uses it to check > - * big-core mode. Other bits are unimplemented so we would > - * prefer to get unimplemented message on POWER10 if it were > - * used anywhere. > - */ > - if (pc->big_core) { > - return PPC_BIT(63); > - } else { > - return 0; > - } > - } > - /* fallthru */ > - > - default: > - qemu_log_mask(LOG_UNIMP, "mfSPRD: Unimplemented SPRC:0x" > - TARGET_FMT_lx"\n", sprc); > - break; > - } > return 0; > } > > void helper_store_sprd(CPUPPCState *env, target_ulong val) > { > - target_ulong sprc = env->spr[SPR_POWER_SPRC]; > PowerPCCPU *cpu = env_archcpu(env); > - PnvCore *pc = pnv_cpu_state(cpu)->pnv_core; > - int nr; > - > - if (pc->big_core) { > - pc = pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x1); > - } > + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); > > - switch (sprc & 0x3e0) { > - case 0: /* SCRATCH0-3 */ > - case 1: /* SCRATCH4-7 */ > - /* > - * Log stores to SCRATCH, because some firmware uses these for > - * debugging and logging, but they would normally be read by the BMC, > - * which is not implemented in QEMU yet. This gives a way to get at the > - * information. Could also dump these upon checkstop. > - */ > - nr = (sprc >> 3) & 0x7; > - pc->scratch[nr] = val; > - break; > - default: > - qemu_log_mask(LOG_UNIMP, "mtSPRD: Unimplemented SPRC:0x" > - TARGET_FMT_lx"\n", sprc); > - break; > + if (pcc->store_sprd) { > + return pcc->store_sprd(env, val); > } > } >