From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH 7/9] target/arm: Make FPSCR.LTPSIZE writable for MVE
Date: Mon, 24 May 2021 09:56:44 -0700 [thread overview]
Message-ID: <23a65549-1a53-c5c3-18c3-9e3f2355ce3b@linaro.org> (raw)
In-Reply-To: <20210520152840.24453-8-peter.maydell@linaro.org>
On 5/20/21 8:28 AM, Peter Maydell wrote:
> The M-profile FPSCR has an LTPSIZE field, but if MVE is not
> implemented it is read-only and always reads as 4; this is how QEMU
> currently handles it.
>
> Make the field writable when MVE is implemented.
>
> We can safely add the field to the MVE migration struct because
> currently no CPUs enable MVE and so the migration struct is never
> used.
>
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> ---
> target/arm/cpu.h | 3 ++-
> target/arm/machine.c | 1 +
> target/arm/vfp_helper.c | 9 ++++++---
> 3 files changed, 9 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2021-05-24 17:13 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-20 15:28 [PATCH 0/9] target/arm: MVE preliminaries Peter Maydell
2021-05-20 15:28 ` [PATCH 1/9] target/arm: Add isar feature check functions for MVE Peter Maydell
2021-05-24 15:21 ` Richard Henderson
2021-05-20 15:28 ` [PATCH 2/9] target/arm: Update feature checks for insns which are "MVE or FP" Peter Maydell
2021-05-24 15:32 ` Richard Henderson
2021-05-20 15:28 ` [PATCH 3/9] target/arm: Move fpsp/fpdp isar check into callers of do_vfp_2op_sp/dp Peter Maydell
2021-05-24 16:24 ` Richard Henderson
2021-05-20 15:28 ` [PATCH 4/9] target/arm: Add MVE check to VMOV_reg_sp and VMOV_reg_dp Peter Maydell
2021-05-24 16:31 ` Richard Henderson
2021-05-20 15:28 ` [PATCH 5/9] target/arm: Fix return values in fp_sysreg_checks() Peter Maydell
2021-05-24 16:36 ` Richard Henderson
2021-05-20 15:28 ` [PATCH 6/9] target/arm: Implement M-profile VPR register Peter Maydell
2021-05-24 16:51 ` Richard Henderson
2021-05-20 15:28 ` [PATCH 7/9] target/arm: Make FPSCR.LTPSIZE writable for MVE Peter Maydell
2021-05-24 16:56 ` Richard Henderson [this message]
2021-05-20 15:28 ` [PATCH 8/9] target/arm: Enable FPSCR.QC bit " Peter Maydell
2021-05-24 16:59 ` Richard Henderson
2021-05-24 17:08 ` Peter Maydell
2021-05-20 15:28 ` [PATCH 9/9] target/arm: Allow board models to specify initial NS VTOR Peter Maydell
2021-05-24 17:05 ` Richard Henderson
2021-05-20 15:45 ` [PATCH 0/9] target/arm: MVE preliminaries no-reply
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