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([2804:7f0:b401:1758:f7d8:1e03:a6d:61a0]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-716b4d54ea2sm5793276a12.54.2024.06.24.11.14.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Jun 2024 11:14:32 -0700 (PDT) Subject: Re: [PATCH v2 2/2] target/arm: Enable FEAT_Debugv8p8 for -cpu max To: Peter Maydell Cc: qemu-devel@nongnu.org, alex.bennee@linaro.org, richard.henderson@linaro.org, philmd@linaro.org References: <20240621143903.3598230-1-gustavo.romero@linaro.org> <20240621143903.3598230-3-gustavo.romero@linaro.org> From: Gustavo Romero Message-ID: <23a6ff61-2b30-dc45-ffe2-ed24e53a19f4@linaro.org> Date: Mon, 24 Jun 2024 15:14:29 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=gustavo.romero@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.232, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Peter, On 6/24/24 10:27 AM, Peter Maydell wrote: > On Fri, 21 Jun 2024 at 15:39, Gustavo Romero wrote: >> >> Enable FEAT_Debugv8p8 for max CPU. This feature is out of scope for QEMU >> since it concerns the external debug interface for JTAG, but is >> mandatory in Armv8.8 implementations, hence it is reported as supported >> in the ID registers. >> >> Signed-off-by: Gustavo Romero >> --- >> target/arm/tcg/cpu32.c | 6 +++--- >> target/arm/tcg/cpu64.c | 2 +- >> 2 files changed, 4 insertions(+), 4 deletions(-) >> >> diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c >> index b155a0136f..a1273a73a3 100644 >> --- a/target/arm/tcg/cpu32.c >> +++ b/target/arm/tcg/cpu32.c >> @@ -82,8 +82,8 @@ void aa32_max_features(ARMCPU *cpu) >> cpu->isar.id_pfr2 = t; >> >> t = cpu->isar.id_dfr0; >> - t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */ >> - t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */ >> + t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ >> + t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */ >> t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ >> cpu->isar.id_dfr0 = t; >> >> @@ -93,7 +93,7 @@ void aa32_max_features(ARMCPU *cpu) >> t = 0x00008000; >> t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1); >> t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1); >> - t = FIELD_DP32(t, DBGDIDR, VERSION, 6); /* Armv8 debug */ >> + t = FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */ >> t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1); >> t = FIELD_DP32(t, DBGDIDR, BRPS, 5); >> t = FIELD_DP32(t, DBGDIDR, WRPS, 3); >> diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c >> index 71e1bfcd4e..fe232eb306 100644 >> --- a/target/arm/tcg/cpu64.c >> +++ b/target/arm/tcg/cpu64.c >> @@ -1253,7 +1253,7 @@ void aarch64_max_tcg_initfn(Object *obj) >> cpu->isar.id_aa64zfr0 = t; >> >> t = cpu->isar.id_aa64dfr0; >> - t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ >> + t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */ >> t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */ >> t = FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */ >> cpu->isar.id_aa64dfr0 = t; >> -- > > We also need to add Feat_Debugv8p8 to the (alphabetically-sorted) > list of emulated features in docs/system/arm/emulation.rst. oh, I forgot it. Thanks, done in v3. Cheers, Gustavo