Re: [PATCH 04/14] target/arm: Implement FEAT_MOPS enable bits

[Richard Henderson <richard.henderson@linaro.org>]

On 9/7/23 09:03, Peter Maydell wrote:
> FEAT_MOPS defines a handful of new enable bits:
>   * HCRX_EL2.MSCEn, SCTLR_EL1.MSCEn, SCTLR_EL2.MSCen:
>     define whether the new insns should UNDEF or not
>   * HCRX_EL2.MCE2: defines whether memops exceptions from
>     EL1 should be taken to EL1 or EL2
> 
> Since we don't sanitise what bits can be written for the SCTLR
> registers, we only need to handle the new bits in HCRX_EL2, and
> define SCTLR_MSCEN for the new SCTLR bit value.
> 
> The precedence of "HCRX bits acts as 0 if SCR_EL3.HXEn is 0" versus
> "bit acts as 1 if EL2 disabled" is not clear from the register
> definition text, but it is clear in the CheckMOPSEnabled()
> pseudocode(), so we follow that.  We'll have to check whether other
> bits we need to implement in future follow the same logic or not.
> 
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> ---
>   target/arm/cpu.h    |  6 ++++++
>   target/arm/helper.c | 28 +++++++++++++++++++++-------
>   2 files changed, 27 insertions(+), 7 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~